Datasheet

© 2009 Microchip Technology Inc. DS39755C-page 41
PIC18F2423/2523/4423/4523
FIGURE 4-4: A/D CONVERSION TIMING
TABLE 4-2: A/D CONVERSION REQUIREMENTS
Param
No.
Symbol Characteristic Min Max Units Conditions
130 T
AD A/D Clock Period PIC18FXXXX 0.8 12.5
(1)
μsTOSC based, VREF ≥ 3.0V
PIC18LFXXXX 1.4 25.0
(1)
μsVDD = 3.0V;
T
OSC based, VREF full range
PIC18FXXXX — 1 μs A/D RC mode
PIC18LFXXXX — 3 μsVDD = 3.0V; A/D RC mode
131 T
CNV Conversion Time
(not including acquisition time)
(2)
13 14 TAD
132 TACQ Acquisition Time
(3)
1.4 — μs
135 T
SWC Switching Time from Convert → Sample — (Note 4)
137 TDIS Discharge Time 0.2 — μs
Note 1: The time of the A/D clock period is dependent on the device frequency and the T
AD clock divider.
2: ADRES registers may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (V
DD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.
4: On the following cycle of the device clock.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
(1)
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(Note 2)
11 10 9 3 2 1
Note 1: If the A/D clock source is selected as RC, a time of T
CY is added before the A/D clock starts. This allows the SLEEP instruction
to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
. . .
. . .
TCY
0