Datasheet

PIC18F2423/2523/4423/4523

3.0 SPECIAL FEATURES OF THE

CPU

3.1 Device ID Registers

The Device ID registers are read-only registers. They

identify the device type and revision for device pro-

grammers and can be read by firmware using table

reads.

TABLE 3-1: DEVICE IDs

Note: For additional details on the Configuration

bits, refer to Section 23.1 “Configuration

Bits” in the “PIC18F2420/2520/4420/4520

Data Sheet” (DS39631). Device ID informa-

tion presented in this section is for the

PIC18F2423/2523/4423/4523 devices only.

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Default/

Unprogrammed

Value

3FFFFEh DEVID1

(1)

DEV3 DEV2 DEV1 DEV0 REV3 REV2 REV1 REV0 xxxx xxxx

(2)

3FFFFFh DEVID2

(1)

DEV11 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 xxxx xxxx

(2)

Legend: x = unknown, u = unchanged, — = unimplemented. Shaded cells are unimplemented, read as ‘0’.

Note 1: DEVID registers are read-only and cannot be programmed by the user.

2: See Register 3-1 and Register 3-2 for DEVID1 and DEVID2 values.

RRRRRRRR

DEV3 DEV2 DEV1 DEV0 REV3 REV2 REV1 REV0

bit 7 bit 0

Legend:

R = Read-only bit P = Programmable bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed u = Unchanged from programmed state

bit 7-4 DEV<3:0>: Device ID bits

1101 = PIC18F4423

1001 = PIC18F4523

0101 = PIC18F2423

0001 = PIC18F2523

bit 3-0 REV<3:0>: Revision ID bits

These bits are used to indicate the device revision.