Datasheet

© 2009 Microchip Technology Inc. DS39755C-page 3
PIC18F2423/2523/4423/4523
Power Management Features:
Run: CPU on, Peripherals on
Idle: CPU off, Peripherals on
Sleep: CPU off, Peripherals off
Ultra Low 50 nA Input Leakage
Run mode Currents Down to 11 μA Typical
Idle mode Currents Down to 2.5 μA Typical
Sleep mode Current Down to 100 μA Typical
Timer1 Oscillator: 900 nA, 32 kHz, 2V
Watchdog Timer: 1.4 μA, 2V Typical
Two-Speed Oscillator Start-up
Flexible Oscillator Structure:
Four Crystal modes, up to 40 MHz
4x Phase Lock Loop (PLL) – Available for Crystal
and Internal Oscillators
Two External RC modes, up to 4 MHz
Two External Clock modes, up to 40 MHz
Internal Oscillator Block:
- Fast wake from Sleep and Idle, 1 μs typical
- 8 user-selectable frequencies, from 31 kHz to 8 MHz
- Provides a complete range of clock speeds,
from 31 kHz to 32 MHz, when used with PLL
- User-tunable to Compensate for Frequency Drift
Secondary Oscillator using Timer1 @ 32 kHz
Fail-Safe Clock Monitor:
- Allows for safe shutdown if peripheral clock stops
Peripheral Highlights:
12-Bit, Up to 13-Channel Analog-to-Digital Converter
module (A/D):
- Auto-acquisition capability
- Conversion available during Sleep mode
Dual Analog Comparators with Input Multiplexing
High-Current Sink/Source 25 mA/25 mA
Three Programmable External Interrupts
Four Input Change Interrupts
Up to Two Capture/Compare/PWM (CCP)
modules, One with Auto-Shutdown (28-pin devices)
Enhanced Capture/Compare/PWM (ECCP) module
(40/44-pin devices only):
- One, two or four PWM outputs
- Selectable polarity
- Programmable dead time
- Auto-shutdown and auto-restart
Peripheral Highlights (Continued):
Master Synchronous Serial Port (MSSP) module
Supporting 3-Wire SPI (all four modes) and I
2
C™
Master and Slave modes
Enhanced USART module:
- Support for RS-485, RS-232 and LIN/J2602
- RS-232 operation using internal oscillator
block (no external crystal required)
- Auto-wake-up on Start bit
- Auto-Baud Detect (ABD)
Special Microcontroller Features:
C Compiler Optimized Architecture: Optional
Extended Instruction Set Designed to Optimize
Re-Entrant Code
100,000 Erase/Write Cycle, Enhanced Flash
Program Memory Typical
1,000,000 Erase/Write Cycle, Data EEPROM
Memory Typical
Flash/Data EEPROM Retention: 100 Years Typical
Self-Programmable under Software Control
Priority Levels for Interrupts
8 x 8 Single-Cycle Hardware Multiplier
Extended Watchdog Timer (WDT): Programmable
Period, from 4 ms to 131s
Single-Supply In-Circuit Serial Programming™
(ICSP™) via Two Pins
In-Circuit Debug (ICD) via Two Pins
Operating Voltage Range: 2.0V to 5.5V
Programmable, 16-Level High/Low-Voltage
Detection (HLVD) module: Supports Interrupt on
High/Low-Voltage Detection
Programmable Brown-out Reset (BOR): With
Software-Enable Option
Note: This document is supplemented by the
“PIC18F2420/2520/4420/4520 Data Sheet”
(DS39631). See Section 1.0 “Device
Overview”.
Device
Program Memory Data Memory
I/O
12-Bit
A/D (ch)
CCP/
ECCP
(PWM)
MSSP
EUSART
Comp.
Timers
8/16-Bit
Flash
(bytes)
# Single-Word
Instructions
SRAM
(bytes)
EEPROM
(bytes)
SPI
Master
I
2
C™
PIC18F2423 16K 8192 768 256 25 10 2/0 Y Y 1 2 1/3
PIC18F2523 32K 16384 1536 256 25 10 2/0 Y Y 1 2 1/3
PIC18F4423 16K 8192 768 256 36 13 1/1 Y Y 1 2 1/3
PIC18F4523 32K 16384 1536 256 36 13 1/1 Y Y 1 2 1/3
28/40/44-Pin, Enhanced Flash Microcontrollers with
12-Bit A/D and nanoWatt Technology