Datasheet

DS39631E-page 405 © 2008 Microchip Technology Inc.
PIC18F2420/2520/4420/4520
CLKO and I/O............................................................344
Clock Synchronization...............................................181
Clock/Instruction Cycle................................................57
EUSART Synchronous Receive
(Master/Slave)...................................................359
EUSART Synchronous Transmission
(Master/Slave)...................................................358
Example SPI Master Mode (CKE = 0).......................349
Example SPI Master Mode (CKE = 1).......................350
Example SPI Slave Mode (CKE = 0).........................351
Example SPI Slave Mode (CKE = 1).........................353
External Clock (All Modes Except PLL) ....................342
Fail-Safe Clock Monitor (FSCM) ...............................262
First Start Bit Timing..................................................189
Full-Bridge PWM Output ...........................................153
Half-Bridge PWM Output...........................................152
High/Low-Voltage Detect Characteristics..................339
High-Voltage Detect Operation (VDIRMAG = 1) .......246
I
2
C Bus Data .............................................................354
I
2
C Bus Start/Stop Bits..............................................354
I
2
C Master Mode (7 or 10-Bit Transmission).............192
I
2
C Master Mode (7-Bit Reception) ........................... 193
I
2
C Slave Mode (10-Bit Reception, SEN = 0)............178
I
2
C Slave Mode (10-Bit Reception, SEN = 1)............183
I
2
C Slave Mode (10-Bit Transmission) ......................179
I
2
C Slave Mode (7-Bit Reception, SEN = 0)..............176
I
2
C Slave Mode (7-Bit Reception, SEN = 1)..............182
I
2
C Slave Mode (7-Bit Transmission) ........................177
I
2
C Slave Mode General Call Address
Sequence (7 or 10-Bit Addressing Mode) .........184
I
2
C Stop Condition Receive or Transmit Mode .........194
Low-Voltage Detect Operation (VDIRMAG = 0)........ 245
Master SSP I
2
C Bus Data .........................................356
Master SSP I
2
C Bus Start/Stop Bits..........................356
Parallel Slave Port (PIC18F4420/4520) ....................348
Parallel Slave Port (PSP) Read ................................121
Parallel Slave Port (PSP) Write.................................121
PWM Auto-Shutdown (PRSEN = 0,
Auto-Restart Disabled)......................................158
PWM Auto-Shutdown (PRSEN = 1,
Auto-Restart Enabled)....................................... 158
PWM Direction Change.............................................155
PWM Direction Change at Near
100% Duty Cycle...............................................155
PWM Output..............................................................144
Repeated Start Condition.......................................... 190
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer .....................................345
Send Break Character Sequence ............................. 216
Slave Synchronization...............................................167
Slow Rise Time (MCLR
Tied to VDD,
V
DD Rise > TPWRT) .............................................47
SPI Mode (Master Mode) .......................................... 166
SPI Mode (Slave Mode, CKE = 0)............................. 168
SPI Mode (Slave Mode, CKE = 1)............................. 168
Synchronous Reception (Master Mode, SREN)........219
Synchronous Transmission.......................................217
Synchronous Transmission (Through TXEN) ...........218
Time-out Sequence on POR w/PLL Enabled
(MCLR
Tied to VDD) ............................................47
Time-out Sequence on Power-up
(MCLR
Not Tied to VDD, Case 1) ........................ 46
Time-out Sequence on Power-up
(MCLR
Not Tied to VDD, Case 2) ........................ 46
Time-out Sequence on Power-up
(MCLR
Tied to VDD, VDD Rise < TPWRT) ............ 46
Timer0 and Timer1 External Clock ........................... 346
Transition for Entry to Idle Mode................................. 38
Transition for Entry to SEC_RUN Mode ..................... 35
Transition for Entry to Sleep Mode ............................. 37
Transition for Two-Speed Start-up
(INTOSC to HSPLL) ......................................... 260
Transition for Wake from Idle to
Run Mode ........................................................... 38
Transition for Wake from Sleep (HSPLL) ................... 37
Transition from RC_RUN Mode to
PRI_RUN Mode .................................................. 36
Transition from SEC_RUN Mode to
PRI_RUN Mode (HSPLL) ................................... 35
Transition to RC_RUN Mode ...................................... 36
Timing Diagrams and Specifications................................. 342
A/D Conversion Requirements ................................. 360
Capture/Compare/PWM (CCP)
Requirements ................................................... 347
CLKO and I/O Requirements.................................... 344
EUSART Synchronous Receive
Requirements ................................................... 359
EUSART Synchronous Transmission
Requirements ................................................... 358
Example SPI Mode Requirements
(Master Mode, CKE = 0)................................... 349
Example SPI Mode Requirements
(Master Mode, CKE = 1)................................... 350
Example SPI Mode Requirements
(Slave Mode, CKE = 0)..................................... 352
Example SPI Mode Requirements
(Slave Mode, CKE = 1)..................................... 353
External Clock Requirements ................................... 342
I
2
C Bus Data Requirements (Slave Mode) ............... 355
Master SSP I
2
C Bus Data
Requirements ................................................... 357
Master SSP I
2
C Bus Start/Stop Bits
Requirements ................................................... 356
Parallel Slave Port Requirements
(PIC18F4420/4520) .......................................... 348
PLL Clock ................................................................. 343
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements......................................... 345
Timer0 and Timer1 External Clock
Requirements ................................................... 346
Top-of-Stack Access........................................................... 54
TRISE Register
PSPMODE Bit........................................................... 114
TSTFSZ ............................................................................ 307
Two-Speed Start-up.................................................. 249, 260
Two-Word Instructions
Example Cases........................................................... 58
TXSTA Register
BRGH Bit .................................................................. 205
V
Voltage Reference Specifications ..................................... 338