Datasheet

PIC18F2420/2520/4420/4520
DS39631E-page 358 © 2008 Microchip Technology Inc.
FIGURE 26-22: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 26-23: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
TABLE 26-24: A/D CONVERTER CHARACTERISTICS: PIC18F2420/2520/4420/4520 (INDUSTRIAL)
PIC18LF2420/2520/4420/4520 (INDUSTRIAL)
Param.
No.
Symbol Characteristic Min Max Units Conditions
125 TdtV2ckl SYNC RCV (MASTER & SLAVE)
Data Hold before CK ↓ (DT hold time) 10 — ns
126 TckL2dtl Data Hold after CK ↓ (DT hold time) 15 — ns
Param
No.
Symbol Characteristic Min Typ Max Units Conditions
A01 N
R Resolution — — 10 bit ΔVREF ≥ 3.0V
A03 EIL Integral Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V
A04 E
DL Differential Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V
A06 EOFF Offset Error — — <±2.0 LSb ΔVREF ≥ 3.0V
A07 EGN Gain Error — — <±1 LSb ΔVREF ≥ 3.0V
A10 — Monotonicity Guaranteed
(1)
—VSS ≤ VAIN ≤ VREF
A20 ΔVREF Reference Voltage Range
(V
REFH – VREFL)
1.8
3
—
—
—
—
V
V
V
DD < 3.0V
V
DD ≥ 3.0V
A21 V
REFH Reference Voltage High VSS —VREFH V
A22 VREFL Reference Voltage Low VSS – 0.3V — VDD – 3.0V V
A25 V
AIN Analog Input Voltage VREFL —VREFH V
A30 Z
AIN Recommended Impedance of
Analog Voltage Source
——2.5kΩ
A40 I
AD A/D Current from
V
DD
PIC18FXXXX — 180 — μA Average current during
conversion
PIC18LFXX20 — 90 — μA
A50 I
REF VREF Input Current
(2)
—
—
—
—
5
150
μA
μA
During VAIN acquisition.
During A/D conversion
cycle.
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing
codes.
2: V
REFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source.
V
REFL current is from RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source.
125
126
RC6/TX/CK
RC7/RX/DT
pin
pin
Note: Refer to Figure 26-5 for load conditions.