Datasheet

PIC18F2331/2431/4331/4431
DS39616D-page 90  2010 Microchip Technology Inc.
8.4 Erasing Flash Program Memory
The minimum erase block is 32 words or 64 bytes.
Larger blocks of program memory can be bulk erased
only through the use of an external programmer or
ICSP control. Word erase in the Flash array is not
supported.
When initiating an erase sequence from the micro-
controller itself, a block of 64 bytes of program memory
is erased. The Most Significant 16 bits of the
TBLPTR<21:6> point to the block being erased;
TBLPTR<5:0> are ignored.
The EECON1 register commands the erase operation.
The EEPGD bit (EECON1<7>) must be set to point to
the Flash program memory. The WREN bit
(EECON1<2>) must be set to enable write operations.
The FREE bit (EECON1<4>) is set to select an erase
operation.
For protection, the write initiate sequence using
EECON2 must be used.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
8.4.1 FLASH PROGRAM MEMORY
ERASE SEQUENCE
The sequence of events for erasing a block of internal
program memory location is:
1. Load the Table Pointer with the address of the
row being erased.
2. Set the EECON1 register for the erase
operation:
- set the EEPGD bit to point to program memory;
- clear the CFGS bit to access program memory;
- set the WREN bit to enable writes;
- set the FREE bit to enable the erase.
3. Disable interrupts.
4. Write 55h to EECON2.
5. Write 0AAh to EECON2.
6. Set the WR bit. This will begin the row erase
cycle.
7. The CPU will stall for the duration of the erase
(about 2 ms using internal timer).
8. Execute a NOP.
9. Re-enable interrupts.
EXAMPLE 8-2: ERASING A FLASH PROGRAM MEMORY ROW
MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
ERASE_ROW
BSF EECON1, EEPGD ; point to Flash program memory
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BSF EECON1, FREE ; enable Row Erase operation
BCF INTCON, GIE ; disable interrupts
MOVLW 55h
MOVWF EECON2 ; write 55H
Required MOVLW 0AAh
Sequence MOVWF EECON2 ; write 0AAH
BSF EECON2, WR ; start erase (CPU stall)
NOP
BSF INTCON, GIE ; re-enable interrupts