Datasheet

 2010 Microchip Technology Inc. DS39616D-page 71
PIC18F2331/2431/4331/4431
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0000 q000
LVDCON
— — IRVST LVDEN LVDL 3 LVDL2 LVDL1 LVDL0 --00 0101
WDTCON WDTW
— — — — — —SWDTEN0--- ---0
RCON IPEN
— —RITO PD POR BOR 0--1 11q0
TMR1H Timer1 Register High Byte xxxx xxxx
TMR1L Timer1 Register Low Byte xxxx xxxx
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 0000 0000
TMR2 Timer2 Register 0000 0000
PR2 Timer2 Period Register 1111 1111
T2CON
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000
SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx
SSPADD SSP Address Register in I
2
C™ Slave mode. SSP Baud Rate Reload Register in I
2
C Master mode. 0000 0000
SSPSTAT SMP CKE D/A
PSR/WUA BF 0000 0000
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000
ADRESH A/D Result Register High Byte xxxx xxxx
ADRESL A/D Result Register Low Byte xxxx xxxx
ADCON0
— — ACONV ACSCH ACMOD1 ACMOD0 GO/DONE ADON --00 0000
ADCON1 VCFG1 VCFG0
— FIFOEN BFEMT BFOVFL ADPNT1 ADPNT0 00-0 0000
ADCON2 ADFM ACQT3 ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0000 0000
ADCON3 ADRS1 ADRS0
— SSRC4 SSRC3 SSRC2 SSRC1 SSRC0 00-0 0000
ADCHS GDSEL1 GDSEL0 GBSEL1 GBSEL0 GCSEL1 GCSEL0 GASEL1 GASEL0 0000 0000
CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx
CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx
CCP1CON
— — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000
CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx
CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx
CCP2CON
— — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000
ANSEL1
— — — — — — —ANS8
(4)
---- ---1
ANSEL0 ANS7
(4)
ANS6
(4)
ANS5
(4)
ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111
T5CON T5SEN RESEN
(4)
T5MOD T5PS1 T5PS0 T5SYNC TMR5CS TMR5ON 0000 0000
QEICON VELM
QERR UP/DOWN QEIM2 QEIM1 QEIM0 PDEC1 PDEC0 0000 0000
SPBRGH EUSART Baud Rate Generator Register High Byte 0000 0000
SPBRG EUSART Baud Rate Generator Register Low Byte 0000 0000
RCREG EUSART Receive Register 0000 0000
TXREG EUSART Transmit Register 0000 0000
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000X
BAUDCON
— RCIDL — SCKP BRG16 — WUE ABDEN -1-1 0-00
TABLE 6-2: REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented.
Note 1: RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator modes only and read
‘0’ in all other oscillator modes.
2: RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.
3: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
4: These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as ‘0’.
5: The RE3 port bit is only available for PIC18F4331/4431 devices when the MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’; otherwise, RE3
reads ‘0’. This bit is read-only.