Datasheet
PIC18F2331/2431/4331/4431
DS39616D-page 70 2010 Microchip Technology Inc.
TABLE 6-2: REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
TOSU
— — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000
TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000
TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000
STKPTR STKFUL STKUNF
— SP4 SP3 SP2 SP1 SP0 00-0 0000
PCLATU
— —bit 21
(3)
Holding Register for PC<20:16> ---0 0000
PCLATH Holding Register for PC<15:8> 0000 0000
PCL PC Low Byte (PC<7:0>) 0000 0000
TBLPTRU
— —bit 21
(3)
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000
TABLAT Program Memory Table Latch 0000 0000
PRODH Product Register High Byte xxxx xxxx
PRODL Product Register Low Byte xxxx xxxx
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x
INTCON2 RBPU
INTEDG0 INTEDG1 INTEDG2 —TMR0IP—RBIP1111 -1-1
INTCON3 INT2IP INT1IP
— INT2IE INT1IE — INT2IF INT1IF 11-0 0-00
INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A
PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 offset by W (not a physical register) N/A
FSR0H
— — — — Indirect Data Memory Address Pointer 0 High ---- xxxx
FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx
WREG Working Register xxxx xxxx
INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A
PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 offset by W (not a physical register) N/A
FSR1H
— — — — Indirect Data Memory Address Pointer 1 High Byte ---- 0000
FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx
BSR
— — — — Bank Select Register ---- 0000
INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A
PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 offset by W (not a physical register) N/A
FSR2H
— — — — Indirect Data Memory Address Pointer 2 High Byte ---- 0000
FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx
STATUS
— — —NOVZDCC---x xxxx
TMR0H Timer0 Register High Byte 0000 0000
TMR0L Timer0 Register Low Byte xxxx xxxx
T0CON TMR0ON T016BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented.
Note 1: RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator modes only and read
‘0’ in all other oscillator modes.
2: RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.
3: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
4: These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as ‘0’.
5: The RE3 port bit is only available for PIC18F4331/4431 devices when the MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’; otherwise, RE3
reads ‘0’. This bit is read-only.