Datasheet

PIC18F2331/2431/4331/4431
DS39616D-page 56  2010 Microchip Technology Inc.
ADRESH 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu
ADRESL 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 2331 2431 4331 4431 --00 0000 --00 0000 --uu uuuu
ADCON1 2331 2431 4331 4431 00-0 0000 00-0 0000 uu-u uuuu
ADCON2 2331
2431 4331 4431 0000 0000 0000 0000 uuuu uuuu
ADCON3 2331
2431 4331 4431 00-0 0000 00-0 0000 uu-u uuuu
ADCHS 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu
CCPR1H 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1L 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 2331 2431
4331 4431 --00 0000 --00 0000 --uu uuuu
CCPR2H 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR2L 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu
CCP2CON 2331 2431 4331 4431 --00 0000 --00 0000 --uu uuuu
ANSEL1 2331
2431 4331 4431 ---- ---1 ---- ---1 ---- ---u
ANSEL0 2331
2431 4331 4431 1111 1111 1111 1111 uuuu uuuu
T5CON 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu
QEICON 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu
SPBRGH 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu
SPBRG 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu
RCREG 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu
TXREG 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu
TXSTA 2331 2431 4331 4431 0000 -010 0000 -010 uuuu -uuu
RCSTA 2331 2431 4331 4431 0000 000x 0000 000x uuuu uuuu
BAUDCON 2331 2431 4331 4431 -1-1 0-00 -1-1 0-00 -u-u u-uu
EEADR 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu
EEDATA 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu
EECON2 2331 2431 4331 4431 0000 0000 0000 0000 0000 0000
EECON1 2331 2431 4331 4431 xx-0 x000 uu-0 u000 uu-0 u000
IPR3 2331 2431 4331 4431 ---1 1111 ---1 1111 ---u uuuu
PIE3 2331 2431 4331 4431 ---0 0000 ---0 0000 ---u uuuu
PIR3 2331 2431 4331 4431 ---0 0000 ---0 0000 ---u uuuu
TABLE 5-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR
Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 5-2 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: Bit 3 of PORTE and LATE are enabled if MCLR
functionality is disabled. When not enabled as the PORTE
pin, they are disabled and read as ‘0’. The 28-pin devices do not have only RE3 implemented.