Datasheet

PIC18F2331/2431/4331/4431
DS39616D-page 356  2010 Microchip Technology Inc.
FIGURE 26-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
TABLE 26-14: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol Characteristic Min Max Units Conditions
70 TssL2scH,
TssL2scL
SS
 to SCK  or SCK  Input TCY —ns
71 TscH SCK Input High Time Continuous 1.25 T
CY + 30 — ns
71A Single byte 40 — ns (Note 1)
72 TscL SCK Input Low Time Continuous 1.25 T
CY + 30 — ns
72A Single byte 40 — ns (Note 1)
73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)
74 TscH2diL,
TscL2diL
Hold Time of SDI Data Input to SCK Edge 40 — ns
75 TdoR SDO Data Output Rise Time PIC18FXX31 — 25 ns
PIC18LFXX31 — 45 ns
76 TdoF SDO Data Output Fall Time — 25 ns
77 TssH2doZ SS
 to SDO Output High-Impedance 10 50 ns
80 TscH2doV,
TscL2doV
SDO Data Output Valid after SCK
Edge
PIC18FXX31 — 50 ns
PIC18LFXX31 — 100 ns
82 TssL2doV SDO Data Output Valid after SS

Edge
PIC18FXX31 — 50 ns
PIC18LFXX31 — 100 ns
83 TscH2ssH,
TscL2ssH
SS
 after SCK Edge 1.5 TCY + 40 — ns
Note 1: Requires the use of Parameter 73A.
2: Only if Parameter 71A and 72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
82
SDI
74
75, 76
MSb bit 6 - - - - - -1 LSb
77
bit 6 - - - -1 LSb In
80
83
MSb In