Datasheet

PIC18F2331/2431/4331/4431
DS39616D-page 292  2010 Microchip Technology Inc.
BCF Bit Clear f
Syntax: [ label ] BCF f,b[,a]
Operands: 0  f  255
0  b  7
a [0,1]
Operation: 0  f<b>
Status Affected: None
Encoding: 1001 bbba ffff ffff
Description: Bit ‘b’ in register, ‘f’, is cleared. If ‘a’ is
‘0’, the Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
BCF FLAG_REG, 7
Before Instruction
FLAG_REG = 0xC7
After Instruction
FLAG_REG = 0x47
BN Branch if Negative
Syntax: [ label ] BN n
Operands: -128  n  127
Operation: if Negative bit is ‘1’,
(PC) + 2 + 2n  PC
Status Affected: None
Encoding: 1110 0110 nnnn nnnn
Description: If the Negative bit is ‘1’, then the
program will branch.
The 2’s complement number, ‘2n’, is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
‘n’
Process
Data
No
operation
Example:
HERE BN Jump
Before Instruction
PC = address (HERE)
After Instruction
If Negative = 1;
PC = address (Jump)
If Negative = 0;
PC = address (HERE + 2)