Datasheet

PIC18F2331/2431/4331/4431
DS39616D-page 212  2010 Microchip Technology Inc.
19.3 SSP I
2
C Operation
The SSP module, in I
2
C mode, fully implements all slave
functions except general call support and provides
interrupts on Start and Stop bits in hardware to facilitate
firmware implementations of the master functions. The
SSP module implements the standard mode
specifications, as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the SCK/
SCL pin, which is the clock (SCL), and the SDI/SDA
pin, which is the data (SDA). The user must configure
these pins as inputs or outputs through the
TRISC<5:4> or TRISD<3:2> bits.
The SSP module functions are enabled by setting SSP
Enable bit SSPEN (SSPCON<5>).
FIGURE 19-5: SSP BLOCK DIAGRAM
(I
2
C™ MODE)
The SSP module has five registers for I
2
C operation.
These are the:
• SSP Control Register (SSPCON)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) – Not directly
accessible
• SSP Address Register (SSPADD)
The SSPCON register allows control of the I
2
C opera-
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I
2
C modes to be selected:
•I
2
C Slave mode (7-bit address)
•I
2
C Slave mode (10-bit address)
•I
2
C Slave mode (7-bit address), with Start and
Stop bit interrupts enabled to support Firmware
Controlled Master mode
•I
2
C Slave mode (10-bit address), with Start and
Stop bit interrupts enabled to support Firmware
Controlled Master mode
•I
2
C Start and Stop bit interrupts enabled to
support Firmware Controlled Master mode;
Slave is Idle
Selection of any I
2
C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain,
provided these pins are programmed as inputs by
setting the appropriate TRISC or TRISD bits. Pull-up
resistors must be provided externally to the SCL and
SDA pins for proper operation of the I
2
C module.
Additional information on SSP I
2
C operation can be
found in the “PIC
®
Mid-Range MCU Family Reference
Manual” (DS33023).
19.3.1 SLAVE MODE
In Slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<5:4> or TRISD<3:2> set). The
SSP module will override the input state with the output
data when required (slave-transmitter).
When an address is matched, or the data transfer after
an address match is received, the hardware automati-
cally will generate the Acknowledge (ACK
) pulse and
then load the SSPBUF register with the received value
currently in the SSPSR register.
There are certain conditions that will cause the SSP
module not to give this ACK
pulse. They include (either
or both):
a) The Buffer Full bit, BF (SSPSTAT<0>), was set
before the transfer was received.
b) The SSP Overflow bit, SSPOV (SSPCON<6>),
was set before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit, SSPIF (PIR1<3>), is set.
Table 19-2 shows what happens when a data transfer
byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow
condition. Flag bit, BF, is cleared by reading the
SSPBUF register, while bit, SSPOV, is cleared through
software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I
2
C specification, as well as the requirements of the
SSP module, are shown in timing Parameter 100 and
Parameter 101.
Read Write
SSPSR Reg
Match Detect
SSPADD Reg
SSPBUF Reg
Internal
Data Bus
Addr Match
Set, Reset
S, P bits
(SSPSTAT Reg)
SCK/SCL
(1)
Shift
Clock
MSb
SDI/SDA
(1)
LSb
Note 1: When SSPMX = 1 in CONFIG3H:
SCK/SCL is multiplexed to the RC5 pin, SDA/
SDI is multiplexed to the RC4 pin and SDO is
multiplexed to pin, RC7.
When SSPMX = 0 in CONFIG3H:
SCK/SCL is multiplexed to the RD3 pin, SDA/
SDI is multiplexed to the RD2 pin and SDO is
multiplexed to pin, RD1.
Start and
Stop bit Detect