Datasheet

 2010 Microchip Technology Inc. DS39616D-page 179
PIC18F2331/2431/4331/4431
REGISTER 18-3: PWMCON0: PWM CONTROL REGISTER 0
U-0 R/W-1
(1)
R/W-1
(1)
R/W-1
(1)
R/W-0 R/W-0 R/W-0 R/W-0
— PWMEN2 PWMEN1 PWMEN0 PMOD3
(3)
PMOD2 PMOD1 PMOD0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6-4 PWMEN<2:0>: PWM Module Enable bits
(1)
111 = All odd PWM I/O pins are enabled for PWM output
(2)
110 = PWM1, PWM3 pins are enabled for PWM output
101 = All PWM I/O pins are enabled for PWM output
(2)
100 = PWM0, PWM1, PWM2, PWM3, PWM4 and PWM5 pins are enabled for PWM output
011 = PWM0, PWM1, PWM2 and PWM3 I/O pins are enabled for PWM output
010 = PWM0 and PWM1 pins are enabled for PWM output
001 = PWM1 pin is enabled for PWM output
000 = PWM module is disabled; all PWM I/O pins are general purpose I/O
bit 3-0 PMOD<3:0>: PWM Output Pair Mode bits
For PMOD0:
1 = PWM I/O pin pair (PWM0, PWM1) is in the Independent mode
0 = PWM I/O pin pair (PWM0, PWM1) is in the Complementary mode
For PMOD1:
1 = PWM I/O pin pair (PWM2, PWM3) is in the Independent mode
0 = PWM I/O pin pair (PWM2, PWM3) is in the Complementary mode
For PMOD2:
1 = PWM I/O pin pair (PWM4, PWM5) is in the Independent mode
0 = PWM I/O pin pair (PWM4, PWM5) is in the Complementary mode
For PMOD3:
(3)
1 = PWM I/O pin pair (PWM6, PWM7) is in the Independent mode
0 = PWM I/O pin pair (PWM6, PWM7) is in the Complementary mode
Note 1: Reset condition of the PWMEN bits depends on the PWMPIN Configuration bit.
2: When PWMEN<2:0> = 101, PWM<5:0> outputs are enabled for PIC18F2331/2431 devices; PWM<7:0>
outputs are enabled for PIC18F4331/4431 devices.
When PWMEN<2:0> = 111, PWM Outputs 1, 3 and 5 are enabled in PIC18F2331/2431 devices; PWM
Outputs 1, 3, 5 and 7 are enabled in PIC18F4331/4431 devices.
3: Unimplemented in PIC18F2331/2431 devices; maintain these bits clear.