Datasheet

 2010 Microchip Technology Inc. DS39616D-page 165
PIC18F2331/2431/4331/4431
FIGURE 17-9: QEI INPUTS WHEN SAMPLED BY THE FILTER (DIVIDE RATIO = 1:1)
FIGURE 17-10: QEI MODULE RESET TIMING ON PERIOD MATCH
TCY
QEA Pin
TGD = 3 TCY
QEB Pin
QEA Input
QEB Input
Note 1: The module design allows a quadrature frequency of up to FQEI = FCY/16.
TQEI = 16 TCY
(1)
QEB
QEA
UP/DOWN
IC2QEIF
POSCNT
(1)
1520 1521 1522 1523 1524 1525 1526 1527
Count (+/-)
+1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 [phone] -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
MAXCNT
0000 0001 0002 0003 0004 0003 0002 0001 0000 1527 1526 1525 1524 1523 1522 1521 1520 1519 1518 1517 1516 1515 1514
Q4
(3)
Q1
(4)
Q1
(5)
Position
Counter Load
Forward Reverse
Q1
(5)
IC3DRIF
Note 2 Note 2
Note 1: The POSCNT register is shown in QEI x4 Update mode (POSCNT increments on every rising and every falling edge
of QEA and QEB input signals). Asynchronous external QEA and QEB inputs are synchronized to the T
CY clock by
the input sampling FF in the noise filter (see Figure 17-14).
2: When POSCNT = MAXCNT, POSCNT is reset to ‘0’ on the next QEA rising edge. POSCNT is set to MAXCNT when
POSCNT = 0 (when decrementing), which occurs on the next QEA falling edge.
3: IC2QEIF is generated on the Q4 rising edge.
4: Position counter is loaded with ‘0’ (which is a rollover event in this case) on POSCNT = MAXCNT.
5: Position counter is loaded with MAXCNT value (1527h) on underflow.
6: IC2QEIF must be cleared in software.
Note 6
Q4
(3)
MAXCNT=1527