Datasheet

PIC18F2331/2431/4331/4431
DS39616D-page 154  2010 Microchip Technology Inc.
FIGURE 17-3: INPUT CAPTURE BLOCK DIAGRAM FOR IC2 AND IC3
CAPxBUF
(1,2,3)
CAPxREN
(2)
TMR5
Enable
TMR5
TMR5 Reset
Timer
Reset
Control
Capture
Clock
ICxIF
(1)
Capture Clock/
Q Clocks CAPxM<3:0>
(1)
CAPxBUF_clk
(1)
Reset
Reset/
Interrupt
Decode
Logic
Note 1: IC2 and IC3 are denoted as x = 2 and 3.
2: CAP2BUF is enabled as POSCNT when QEI mode is active.
3: CAP3BUF is enabled as MAXCNT when QEI mode is active.
CAP2/3 Pin
CAP1M<3:0>
(1)
Q Clocks
3
4
FLTCK<2:0>
Prescaler
1, 4, 16
Noise
Filter
and
Mode
Select