Datasheet

PIC18F2331/2431/4331/4431
DS39616D-page 110  2010 Microchip Technology Inc.
REGISTER 10-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — — PTIP IC3DRIP IC2QEIP IC1IP TMR5IP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4 PTIP: PWM Time Base Interrupt Priority bit
1 =High priority
0 = Low priority
bit 3 IC3DRIP: IC3 Interrupt Priority/Direction Change Interrupt Priority bit
IC3 Enabled (CAP3CON<3:0>):
1 = IC3 interrupt high priority
0 = IC3 interrupt low priority
QEI Enabled (QEIM<2:0>):
1 = Change of direction interrupt high priority
0 = Change of direction interrupt low priority
bit 2 IC2QEIP: IC2 Interrupt Priority/QEI Interrupt Priority bit
IC2 Enabled (CAP2CON<3:0>):
1 = IC2 interrupt high priority
0 = IC2 interrupt low priority
QEI Enabled (QEIM<2:0>):
1 =High priority
0 = Low priority
bit 1 IC1IP: IC1 Interrupt Priority bit
1 =High priority
0 = Low priority
bit 0 TMR5IP: Timer5 Interrupt Priority bit
1 =High priority
0 = Low priority