Datasheet

 2010 Microchip Technology Inc. DS39622L-page 9
PIC18F2XXX/4XXX FAMILY
For PIC18F2221/4221 devices, the code memory
space extends from 0000h to 00FFFh (4 Kbytes) in one
4-Kbyte block. For PIC18F2321/4321 devices, the
code memory space extends from 0000h to 01FFFh
(8 Kbytes) in two 4-Kbyte blocks. Addresses, 0000h
through 07FFh, however, define a variable “Boot Block”
region that is treated separately from Block 0. All of
these blocks define code protection boundaries within
the code memory space.
The size of the Boot Block in PIC18F2221/2321/4221/
4321 devices can be configured as 256, 512 or
1024 words (see Figure 2-8). This is done through the
BBSIZ<1:0> bits in the Configuration register,
CONFIG4L (see Figure 2-8). It is important to note that
increasing the size of the Boot Block decreases the
size of Block 0.
TABLE 2-7: IMPLEMENTATION OF CODE
MEMORY
FIGURE 2-8: MEMORY MAP AND THE CODE MEMORY SPACE 
FOR PIC18F2221/2321/4221/4321 DEVICES
Device Code Memory Size (Bytes)
PIC18F2221
000000h-000FFFh (4K)
PIC18F4221
PIC18F2321
000000h-001FFFh (8K)
PIC18F4321
000000h
200000h
3FFFFFh
01FFFFh
Note: Sizes of memory areas are not to scale.
* Boot Block size is determined by the BBSIZ<1:0> bits in the CONFIG4L register.
Code Memory
Unimplemented
Read as ‘0’
Configuration
and ID
Space
MEMORY SIZE/DEVICE
Address
Range
8 Kbytes
(PIC18FX321)
4 Kbytes
(PIC18FX221)
BBSIZ<1:0>
11/10 01 00 11/10/01 00
Boot Block*
1K word
Boot Block*
512 words
Boot Block*
256 words
Boot Block*
512 words
Boot Block*
256 words
000000h
0001FFh
Block 0
1.75K words
Block 0
0.75K words
000200h
0003FFh
Block 0
1.5K words
Block 0
0.5K words
000400h
0007FFh
Block 0
1K word
Block 1
1K word
000800h
000FFFh
Block 1
2K words
001000h
001FFFh
Unimplemented
Reads all ‘0’s
002000h
1FFFFFh
Unimplemented
Reads all ‘0’s