Datasheet

 2010 Microchip Technology Inc. DS39622L-page 43
PIC18F2XXX/4XXX FAMILY
P11A TDRWT Data Write Polling Time 4 — ms
P12 T
HLD2 Input Data Hold Time from MCLR/VPP/RE3  2—s
P13 T
SET2VDD Setup Time to MCLR/VPP/RE3  100 — ns (Note 2)
P14 TVALID Data Out Valid from PGC  10 — ns
P15 T
SET3PGM Setup Time to MCLR/VPP/RE3  2—s (Note 2)
P16 T
DLY8 Delay Between Last PGC  and MCLR/VPP/RE3  0—s
P17 T
HLD3MCLR/VPP/RE3 to VDD  —100ns
P18 T
HLD4MCLR/VPP/RE3 to PGM  0—s
6.0 AC/DC CHARACTERISTICS TIMING REQUIREMENTS 
FOR PROGRAM/VERIFY TEST MODE (CONTINUED)
Standard Operating Conditions
Operating Temperature: 25C is recommended
Param
No.
Sym Characteristic Min Max Units Conditions
Note 1: Do not allow excess time when transitioning MCLR
between VIL and VIHH. This can cause spurious program
executions to occur. The maximum transition time is:
1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP, HS, HS/PLL and XT modes only) + 
2 ms (for HS/PLL mode only) + 1.5 s (for EC mode only)
where TCY is the instruction cycle time, TPWRT is the Power-up Timer period and TOSC is the oscillator period. For
specific values, refer to the Electrical Characteristics section of the device data sheet for the particular device.
2: When ICPRT = 1, this specification also applies to ICV
PP.
3: At 0°C-50°C.