Datasheet
2010 Microchip Technology Inc. DS39622L-page 33
PIC18F2XXX/4XXX FAMILY
WDPS<3:0> CONFIG2H Watchdog Timer Postscaler Select bits
1111 = 1:32,768
1110 = 1:16,384
1101 = 1:8,192
1100 = 1:4,096
1011 = 1:2,048
1010 = 1:1,024
1001 = 1:512
1000 = 1:256
0111 = 1:128
0110 = 1:64
0101 = 1:32
0100 = 1:16
0011 = 1:8
0010 = 1:4
0001 = 1:2
0000 = 1:1
WDTEN CONFIG2H Watchdog Timer Enable bit
1 = WDT is enabled
0 = WDT is disabled (control is placed on the SWDTEN bit)
MCLRE CONFIG3H MCLR
Pin Enable bit
1 =MCLR pin is enabled, RE3 input pin is disabled
0 = RE3 input pin is enabled, MCLR
pin is disabled
LPT1OSC CONFIG3H Low-Power Timer1 Oscillator Enable bit
1 = Timer1 is configured for low-power operation
0 = Timer1 is configured for high-power operation
PBADEN CONFIG3H PORTB A/D Enable bit
1 = PORTB A/D<4:0> pins are configured as analog input channels on Reset
0 = PORTB A/D<4:0> pins are configured as digital I/O on Reset
PBADEN CONFIG3H PORTB A/D Enable bit (PIC18FXX8X devices only)
1 = PORTB A/D<4:0> and PORTB A/D<1:0> pins are configured as analog input
channels on Reset
0 = PORTB A/D<4:0> pins are configured as digital I/O on Reset
CCP2MX CONFIG3H CCP2 MUX bit
1 = CCP2 input/output is multiplexed with RC1
(2)
0 = CCP2 input/output is multiplexed with RB3
DEBUG
CONFIG4L Background Debugger Enable bit
1 = Background debugger is disabled, RB6 and RB7 are configured as general
purpose I/O pins
0 = Background debugger is enabled, RB6 and RB7 are dedicated to In-Circuit
Debug
XINST CONFIG4L Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode are enabled
0 = Instruction set extension and Indexed Addressing mode are disabled
(Legacy mode)
TABLE 5-3: PIC18F2XXX/4XXX FAMILY BIT DESCRIPTIONS (CONTINUED)
Bit Name
Configuration
Words
Description
Note 1: The BBSIZ bits, BBSIZ<1:0> and BBSIZ<2:1> bits, cannot be changed once any of the following
code-protect bits are enabled: CPB or CP0, WRTB or WRT0, EBTRB or EBTR0.
2: Not available in PIC18FXX8X and PIC18F2450/4450 devices.