Datasheet
PIC18F2XXX/4XXX FAMILY
DS39622L-page 32 2010 Microchip Technology Inc.
USBDIV CONFIG1L USB Clock Selection bit
(PIC18F2455/2550/4455/4550, PIC18F2458/2553/4458/4553 and
PIC18F2450/4450 devices only)
Selects the clock source for full-speed USB operation:
1 = USB clock source comes from the 96 MHz PLL divided by 2
0 = USB clock source comes directly from the OSC1/OSC2 oscillator block;
no divide
CPUDIV<1:0> CONFIG1L CPU System Clock Selection bits
(PIC18F2455/2550/4455/4550, PIC18F2458/2553/4458/4553 and
PIC18F2450/4450 devices only)
11 = CPU system clock divided by 4
10 = CPU system clock divided by 3
01 = CPU system clock divided by 2
00 = No CPU system clock divide
PLLDIV<2:0> CONFIG1L Oscillator Selection bits
(PIC18F2455/2550/4455/4550, PIC18F2458/2553/4458/4553 and
PIC18F2450/4450 devices only)
Divider must be selected to provide a 4 MHz input into the 96 MHz PLL:
111 = Oscillator divided by 12 (48 MHz input)
110 = Oscillator divided by 10 (40 MHz input)
101 = Oscillator divided by 6 (24 MHz input)
100 = Oscillator divided by 5 (20 MHz input)
011 = Oscillator divided by 4 (16 MHz input)
010 = Oscillator divided by 3 (12 MHz input)
001 = Oscillator divided by 2 (8 MHz input)
000 = No divide – oscillator used directly (4 MHz input)
VREGEN CONFIG2L USB Voltage Regulator Enable bit
(PIC18F2455/2550/4455/4550, PIC18F2458/2553/4458/4553 and
PIC18F2450/4450 devices only)
1 = USB voltage regulator is enabled
0 = USB voltage regulator is disabled
BORV<1:0> CONFIG2L Brown-out Reset Voltage bits
11 =V
BOR is set to 2.0V
10 =V
BOR is set to 2.7V
01 =V
BOR is set to 4.2V
00 =V
BOR is set to 4.5V
BOREN<1:0> CONFIG2L Brown-out Reset Enable bits
11 = Brown-out Reset is enabled in hardware only (SBOREN is disabled)
10 = Brown-out Reset is enabled in hardware only and disabled in Sleep mode
SBOREN is disabled)
01 = Brown-out Reset is enabled and controlled by software (SBOREN is
enabled)
00 = Brown-out Reset is disabled in hardware and software
PWRTEN CONFIG2L Power-up Timer Enable bit
1 = PWRT is disabled
0 = PWRT is enabled
TABLE 5-3: PIC18F2XXX/4XXX FAMILY BIT DESCRIPTIONS (CONTINUED)
Bit Name
Configuration
Words
Description
Note 1: The BBSIZ bits, BBSIZ<1:0> and BBSIZ<2:1> bits, cannot be changed once any of the following
code-protect bits are enabled: CPB or CP0, WRTB or WRT0, EBTRB or EBTR0.
2: Not available in PIC18FXX8X and PIC18F2450/4450 devices.