Datasheet

 2010 Microchip Technology Inc. DS39622L-page 27
PIC18F2XXX/4XXX FAMILY
FIGURE 4-4: SHIFT OUT DATA HOLDING REGISTER TIMING (0010)
4.5 Verify Data EEPROM
A data EEPROM address may be read via a sequence
of core instructions (4-bit command, ‘0000’) and then
output on PGD via the 4-bit command, ‘0010’ (TABLAT
register). The result may then be immediately
compared to the appropriate data in the programmer’s
memory for verification. Refer to Section 4.4 “Read
Data EEPROM Memory” for implementation details of
reading data EEPROM.
4.6 Blank Check
The term “Blank Check” means to verify that the device
has no programmed memory cells. All memories must
be verified: code memory, data EEPROM, ID locations
and Configuration bits. The Device ID registers
(3FFFFEh:3FFFFFh) should be ignored.
A “blank” or “erased” memory cell will read as ‘1’. There-
fore, Blank Checking a device merely means to verify
that all bytes read as FFh, except the Configuration bits.
Unused (reserved) Configuration bits will read ‘0’ (pro-
grammed). Refer to Figure 4-5 for blank configuration
expect data for the various PIC18F2XXX/4XXX family
devices.
Given that Blank Checking is merely code and data
EEPROM verification with FFh expect data, refer to
Section 4.4 “Read Data EEPROM Memory” and
Section 4.2 “Verify Code Memory and ID Locations”
for implementation details.
FIGURE 4-5: BLANK CHECK FLOW
1234
PGC
P5
PGD
PGD = Input
Shift Data Out
P6
PGD = Output
5678
1234
P5A
91011 13 15161412
Fetch Next 4-Bit Command
0100
PGD = Input
LSb
MSb
12
34
56
1234
nnnn
P14
Yes
No
Start
Blank Check Device
Is
device
blank?
Continue
Abort