Datasheet

PIC18F2XXX/4XXX FAMILY
DS39622L-page 24  2010 Microchip Technology Inc.
4.0 READING THE DEVICE
4.1 Read Code Memory, ID Locations
and Configuration Bits
Code memory is accessed, one byte at a time, via the
4-bit command, ‘1001’ (Table Read, post-increment).
The contents of memory pointed to by the Table Pointer
(TBLPTRU:TBLPTRH:TBLPTRL) are serially output on
PGD.
The 4-bit command is shifted in, LSb first. The read is
executed during the next 8 clocks, then shifted out on
PGD during the last 8 clocks, LSb to MSb. A delay of
P6 must be introduced after the falling edge of the 8th
PGC of the operand to allow PGD to transition from an
input to an output. During this time, PGC must be held
low (see Figure 4-1). This operation also increments
the Table Pointer by one, pointing to the next byte in
code memory for the next read.
This technique will work to read any memory in the
000000h to 3FFFFFh address space, so it also applies
to the reading of the ID and Configuration registers.
TABLE 4-1: READ CODE MEMORY SEQUENCE
FIGURE 4-1: TABLE READ POST-INCREMENT INSTRUCTION TIMING (1001)
4-Bit
Command
Data Payload Core Instruction
Step 1: Set Table Pointer.
0000
0000
0000
0000
0000
0000
0E <Addr[21:16]>
6E F8
0E <Addr[15:8]>
6E F7
0E <Addr[7:0]>
6E F6
MOVLW Addr[21:16]
MOVWF TBLPTRU
MOVLW <Addr[15:8]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
Step 2: Read memory and then shift out on PGD, LSb to MSb.
1001 00 00 TBLRD *+
1234
PGC
P5
PGD
PGD = Input
Shift Data Out
P6
PGD = Output
5678
1234
P5A
9
10 11 13 15 161412
Fetch Next 4-Bit Command
1001
PGD = Input
LSb
MSb
12
34
56
1234
nnnn
P14