Datasheet

PIC18F2XXX/4XXX FAMILY
DS39622L-page 20  2010 Microchip Technology Inc.
3.3 Data EEPROM Programming
Data EEPROM is accessed one byte at a time via an
Address Pointer (register pair: EEADRH:EEADR) and
a data latch (EEDATA). Data EEPROM is written by
loading EEADRH:EEADR with the desired memory
location, EEDATA, with the data to be written and initi-
ating a memory write by appropriately configuring the
EECON1 register. A byte write automatically erases the
location and writes the new data (erase-before-write).
When using the EECON1 register to perform a data
EEPROM write, both the EEPGD and CFGS bits must
be cleared (EECON1<7:6> = 00). The WREN bit must
be set (EECON1<2> = 1) to enable writes of any sort
and this must be done prior to initiating a write
sequence. The write sequence is initiated by setting the
WR bit (EECON1<1> = 1).
The write begins on the falling edge of the 4th PGC
after the WR bit is set. It ends when the WR bit is
cleared by hardware.
After the programming sequence terminates, PGC must
still be held low for the time specified by Parameter P10
to allow high-voltage discharge of the memory array.
FIGURE 3-6: PROGRAM DATA FLOW
FIGURE 3-7: DATA EEPROM WRITE TIMING
Note: Data EEPROM programming is not
available on the the following devices:
PIC18F2410 PIC18F4410
PIC18F2450 PIC18F4450
PIC18F2510 PIC18F4510
PIC18F2515 PIC18F4515
PIC18F2610 PIC18F4610
Start
Start Write
Set Data
Done
No
Yes
Done?
Enable Write
Sequence
Set Address
WR bit
clear?
No
Yes
n
PGC
PGD
PGD = Input
0000
BSF EECON1, WR4-Bit Command
1234
1
21516
P5
P5A
P10
12
n
Poll WR bit, Repeat until Clear
16-Bit Data
Payload
1234
1
21516
123
P5
P5A
4
1 2 15 16
P5 P5A
0000
MOVF EECON1, W, 0
4-Bit Command
0000
4-Bit Command
Shift Out Data
MOVWF TABLAT
PGC
PGD
(see below)
(see Figure 4-4)
PGD = Input PGD = Output
Poll WR bit
P11A