Datasheet

 2010 Microchip Technology Inc. DS39622L-page 11
PIC18F2XXX/4XXX FAMILY
2.4 High-Level Overview of the
Programming Process
Figure 2-10 shows the high-level overview of the
programming process. First, a Bulk Erase is performed.
Next, the code memory, ID locations and data EEPROM
are programmed (selected devices only, see Section 3.3
“Data EEPROM Programming”). These memories are
then verified to ensure that programming was successful.
If no errors are detected, the Configuration bits are then
programmed and verified.
FIGURE 2-10: HIGH-LEVEL
PROGRAMMING FLOW
2.5 Entering and Exiting High-Voltage
ICSP Program/Verify Mode
As shown in Figure 2-11, the High-Voltage ICSP
Program/Verify mode is entered by holding PGC and
PGD low and then raising MCLR/VPP/RE3 to VIHH
(high voltage). Once in this mode, the code memory,
data EEPROM (selected devices only, see Section 3.3
“Data EEPROM Programming”), ID locations and
Configuration bits can be accessed and programmed in
serial fashion. Figure 2-12 shows the exit sequence.
The sequence that enters the device into the Program/
Verify mode places all unused I/Os in the high-impedance
state.
FIGURE 2-11: ENTERING HIGH-VOLTAGE
PROGRAM/VERIFY MODE
FIGURE 2-12: EXITING HIGH-VOLTAGE
PROGRAM/VERIFY MODE
Start
Program Memory
Program IDs
Program Data EE
(1)
Verify Program
Verify IDs
Verify Data
Program
Configuration Bits
Verify
Configuration Bits
Done
Perform Bulk
Erase
Note 1: Selected devices only, see Section 3.3
“Data EEPROM Programming”.
P12
PGD
PGD = Input
PGC
VDD
D110
P13
P1
MCLR/VPP/RE3
MCLR/VPP/RE3
P16
PGD
PGD = Input
PGC
VDD
D110
P17
P1