PIC18F2XXX/4XXX FAMILY Flash Microcontroller Programming Specification 1.0 DEVICE OVERVIEW ICSP method is slightly different than the high-voltage method and these differences are noted where applicable.
PIC18F2XXX/4XXX FAMILY FIGURE 2-1: PIC18F2XXX/4XXX FAMILY PIN DIAGRAMS 28-Pin SPDIP, PDIP, SOIC and SSOP The following devices are included in 28-pin SPDIP, PDIP and SOIC parts: • PIC18F2523 • PIC18F2321 • PIC18F2525 • PIC18F2410 • PIC18F2550 • PIC18F2420 • PIC18F2553 • PIC18F2423 • PIC18F2580 • PIC18F2450 • PIC18F2585 • PIC18F2455 • PIC18F2610 • PIC18F2458 • PIC18F2620 • PIC18F2480 • PIC18F2680 • PIC18F2510 • PIC18F2682 • PIC18F2515 • PIC18F2685 MCLR/VPP/RE3 RA0 RA1 RA2 RA3 RA4 RA5 V
PIC18F2XXX/4XXX FAMILY RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 NC(1)/ICPORTS PIC18F2XXX/4XXX FAMILY PIN DIAGRAMS 44-Pin TQFP • PIC18F4221 • PIC18F4523 • PIC18F4321 • PIC18F4525 • PIC18F4410 • PIC18F4550 • PIC18F4420 • PIC18F4553 • PIC18F4423 • PIC18F4580 • PIC18F4450 • PIC18F4585 • PIC18F4455 • PIC18F4610 • PIC18F4458 • PIC18F4620 • PIC18F4480 • PIC18F4680 • PIC18F4510 • PIC18F4682 • PIC18F4520 • PIC18F4685 44 43 42 41 40 39 38 37 36 35 34 The following devices are included in 40-
PIC18F2XXX/4XXX FAMILY 2.3 TABLE 2-2: Memory Maps For PIC18FX6X0 devices, the code memory space extends from 0000h to 0FFFFh (64 Kbytes) in four 16-Kbyte blocks. For PIC18FX5X5 devices, the code memory space extends from 0000h to 0BFFFFh (48 Kbytes) in three 16-Kbyte blocks. Addresses, 0000h through 07FFh, however, define a “Boot Block” region that is treated separately from Block 0. All of these blocks define code protection boundaries within the code memory space.
PIC18F2XXX/4XXX FAMILY For PIC18F2685/4685 devices, the code memory space extends from 0000h to 017FFFh (96 Kbytes) in five 16-Kbyte blocks. For PIC18F2682/4682 devices, the code memory space extends from 0000h to 0013FFFh (80 Kbytes) in four 16-Kbyte blocks. Addresses, 0000h through 0FFFh, however, define a “Boot Block” region that is treated separately from Block 0. All of these blocks define code protection boundaries within the code memory space. BBSIZ<2:1> bits in the Configuration register, CONFIG4L.
PIC18F2XXX/4XXX FAMILY For PIC18FX5X0/X5X3 devices, the code memory space extends from 000000h to 007FFFh (32 Kbytes) in four 8-Kbyte blocks. For PIC18FX4X5/X4X8 devices, the code memory space extends from 000000h to 005FFFh (24 Kbytes) in three 8-Kbyte blocks. Addresses, 000000h through 0007FFh, however, define a “Boot Block” region that is treated separately from Block 0. All of these blocks define code protection boundaries within the code memory space.
PIC18F2XXX/4XXX FAMILY For PIC18FX4X0/X4X3 devices, the code memory space extends from 000000h to 003FFFh (16 Kbytes) in two 8-Kbyte blocks. Addresses, 000000h through 0003FFh, however, define a “Boot Block” region that is treated separately from Block 0. All of these blocks define code protection boundaries within the code memory space.
PIC18F2XXX/4XXX FAMILY TABLE 2-6: For PIC18F2480/4480 devices, the code memory space extends from 0000h to 03FFFh (16 Kbytes) in one 16-Kbyte block. For PIC18F2580/4580 devices, the code memory space extends from 0000h to 07FFFh (32 Kbytes) in two 16-Kbyte blocks. Addresses, 0000h through 07FFh, however, define a “Boot Block” region that is treated separately from Block 0. All of these blocks define code protection boundaries within the code memory space.
PIC18F2XXX/4XXX FAMILY For PIC18F2221/4221 devices, the code memory space extends from 0000h to 00FFFh (4 Kbytes) in one 4-Kbyte block. For PIC18F2321/4321 devices, the code memory space extends from 0000h to 01FFFh (8 Kbytes) in two 4-Kbyte blocks. Addresses, 0000h through 07FFh, however, define a variable “Boot Block” region that is treated separately from Block 0. All of these blocks define code protection boundaries within the code memory space. CONFIG4L (see Figure 2-8).
PIC18F2XXX/4XXX FAMILY In addition to the code memory space, there are three blocks that are accessible to the user through Table Reads and Table Writes. Their locations in the memory map are shown in Figure 2-9. Users may store identification information (ID) in eight ID registers. These ID registers are mapped in addresses, 200000h through 200007h. The ID locations read out normally, even after code protection is applied. Locations, 300000h through 30000Dh, are reserved for the Configuration bits.
PIC18F2XXX/4XXX FAMILY 2.4 High-Level Overview of the Programming Process 2.5 Entering and Exiting High-Voltage ICSP Program/Verify Mode Figure 2-10 shows the high-level overview of the programming process. First, a Bulk Erase is performed. Next, the code memory, ID locations and data EEPROM are programmed (selected devices only, see Section 3.3 “Data EEPROM Programming”). These memories are then verified to ensure that programming was successful.
PIC18F2XXX/4XXX FAMILY 2.6 Entering and Exiting Low-Voltage ICSP Program/Verify Mode When the LVP Configuration bit is ‘1’ (see Section 5.3 “Single-Supply ICSP Programming”), the Low-Voltage ICSP mode is enabled. As shown in Figure 2-13, Low-Voltage ICSP Program/Verify mode is entered by holding PGC and PGD low, placing a logic high on PGM and then raising MCLR/VPP/RE3 to VIH. In this mode, the RB5/PGM pin is dedicated to the programming function and ceases to be a general purpose I/O pin.
PIC18F2XXX/4XXX FAMILY FIGURE 2-15: TABLE WRITE, POST-INCREMENT TIMING (1101) P2 1 2 3 4 P2A P2B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2 1 3 4 PGC P5A P5 P4 P3 PGD 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 1 1 1 4 C 16-Bit Data Payload 4-Bit Command 1 0 0 n n n n 3 Fetch Next 4-Bit Command PGD = Input Dedicated ICSP/ICD Port (44-Pin TQFP Only) 2.
PIC18F2XXX/4XXX FAMILY 3.0 DEVICE PROGRAMMING Programming includes the ability to erase or write the various memory regions within the device. In all cases, except high-voltage ICSP Bulk Erase, the EECON1 register must be configured in order to operate on a particular memory region. When using the EECON1 register to act on code memory, the EEPGD bit must be set (EECON1<7> = 1) and the CFGS bit must be cleared (EECON1<6> = 0). The WREN bit must be set (EECON1<2> = 1) to enable writes of any sort (e.g.
PIC18F2XXX/4XXX FAMILY 3.1.2 LOW-VOLTAGE ICSP BULK ERASE If it is determined that a data EEPROM erase (selected devices only, see Section 3.3 “Data EEPROM Programming”) must be performed at a supply voltage below the Bulk Erase limit, follow the methodology described in Section 3.3 “Data EEPROM Programming” and write ‘1’s to the array. When using low-voltage ICSP, the part must be supplied by the voltage specified in Parameter D111 if a Bulk Erase is to be executed.
PIC18F2XXX/4XXX FAMILY TABLE 3-3: ERASE CODE MEMORY CODE SEQUENCE 4-Bit Command Data Payload Core Instruction Step 1: Direct access to code memory and enable writes. 0000 0000 0000 8E A6 9C A6 84 A6 BSF BCF BSF EECON1, EEPGD EECON1, CFGS EECON1, WREN CLRF CLRF CLRF TBLPTRU TBLPTRH TBLPTRL Step 2: Point to first row in code memory. 0000 0000 0000 6A F8 6A F7 6A F6 Step 3: Enable erase and erase single row.
PIC18F2XXX/4XXX FAMILY 3.2 Code Memory Programming Programming code memory is accomplished by first loading data into the write buffer and then initiating a programming sequence. The write and erase buffer sizes, shown in Table 3-4, can be mapped to any location of the same size, beginning at 000000h. The actual memory write sequence takes the contents of this buffer and programs the proper amount of code memory that contains the Table Pointer.
PIC18F2XXX/4XXX FAMILY FIGURE 3-4: PROGRAM CODE MEMORY FLOW Start N=1 LoopCount = 0 Configure Device for Writes Load 2 Bytes to Write Buffer at N=N+1 All bytes written? No Yes N=1 LoopCount = LoopCount + 1 Start Write Sequence and Hold PGC High until Done and Wait P9 Hold PGC Low for Time P10 All locations done? No Yes Done TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING (1111) FIGURE 3-5: P10 1 2 3 4 1 3 2 4 5 6 15 16 1 2 3 4 PGC 2 3 P5A P5 PGD 1 P9 1 1 1
PIC18F2XXX/4XXX FAMILY 3.2.1 MODIFYING CODE MEMORY The previous programming example assumed that the device had been Bulk Erased prior to programming (see Section 3.1.1 “High-Voltage ICSP Bulk Erase”). It may be the case, however, that the user wishes to modify only a section of an already programmed device. The appropriate number of bytes required for the erase buffer must be read out of code memory (as described in Section 4.2 “Verify Code Memory and ID Locations”) and buffered.
PIC18F2XXX/4XXX FAMILY 3.3 Data EEPROM Programming Note: After the programming sequence terminates, PGC must still be held low for the time specified by Parameter P10 to allow high-voltage discharge of the memory array.
PIC18F2XXX/4XXX FAMILY TABLE 3-7: PROGRAMMING DATA MEMORY 4-Bit Command Data Payload Core Instruction Step 1: Direct access to data EEPROM. 0000 0000 9E A6 9C A6 BCF BCF EECON1, EEPGD EECON1, CFGS MOVLW MOVWF MOVLW MOVWF EEADR EEADRH MOVLW MOVWF EEDATA BSF EECON1, WREN BSF EECON1, WR Step 2: Set the data EEPROM Address Pointer. 0000 0000 0000 0000 0E 6E OE 6E A9 AA Step 3: Load the data to be written.
PIC18F2XXX/4XXX FAMILY 3.4 ID Location Programming The ID locations are programmed much like the code memory. The ID registers are mapped in addresses, 200000h through 200007h. These locations read out normally even after code protection. Note: Table 3-8 demonstrates the code sequence required to write the ID locations. In order to modify the ID locations, refer to the methodology described in Section 3.2.1 “Modifying Code Memory”.
PIC18F2XXX/4XXX FAMILY 3.5 Boot Block Programming 3.6 The code sequence detailed in Table 3-5 should be used, except that the address used in “Step 2” will be in the range of 000000h to 0007FFh. Configuration Bits Programming Unlike code memory, the Configuration bits are programmed a byte at a time. The Table Write, Begin Programming 4-bit command (‘1111’) is used, but only 8 bits of the following 16-bit payload will be written.
PIC18F2XXX/4XXX FAMILY 4.0 READING THE DEVICE 4.1 Read Code Memory, ID Locations and Configuration Bits The 4-bit command is shifted in, LSb first. The read is executed during the next 8 clocks, then shifted out on PGD during the last 8 clocks, LSb to MSb. A delay of P6 must be introduced after the falling edge of the 8th PGC of the operand to allow PGD to transition from an input to an output. During this time, PGC must be held low (see Figure 4-1).
PIC18F2XXX/4XXX FAMILY 4.2 Verify Code Memory and ID Locations The verify step involves reading back the code memory space and comparing it against the copy held in the programmer’s buffer. Memory reads occur a single byte at a time, so two bytes must be read to compare against the word in the programmer’s buffer. Refer to Section 4.1 “Read Code Memory, ID Locations and Configuration Bits” for implementation details of reading code memory.
PIC18F2XXX/4XXX FAMILY 4.3 FIGURE 4-3: Verify Configuration Bits READ DATA EEPROM FLOW A configuration address may be read and output on PGD via the 4-bit command, ‘1001’. Configuration data is read and written in a byte-wise fashion, so it is not necessary to merge two bytes into a word prior to a compare. The result may then be immediately compared to the appropriate configuration data in the programmer’s memory for verification. Refer to Section 4.
PIC18F2XXX/4XXX FAMILY FIGURE 4-4: 1 SHIFT OUT DATA HOLDING REGISTER TIMING (0010) 2 3 4 1 2 3 4 5 6 7 9 8 10 11 12 13 14 15 16 1 2 3 4 PGC P5 P5A P6 P14 PGD 0 1 0 LSb 1 0 2 3 4 5 6 Shift Data Out PGD = Input 4.5 Verify Data EEPROM A data EEPROM address may be read via a sequence of core instructions (4-bit command, ‘0000’) and then output on PGD via the 4-bit command, ‘0010’ (TABLAT register).
PIC18F2XXX/4XXX FAMILY 5.0 CONFIGURATION WORD The PIC18F2XXX/4XXX family devices have several Configuration Words. These bits can be set or cleared to select various device configurations. All other memory areas should be programmed and verified prior to setting the Configuration Words. These bits may be read out normally, even after read or code protection. See Table 5-1 for a list of Configuration bits and Device IDs, and Table 5-3 for the Configuration bit descriptions. 5.
PIC18F2XXX/4XXX FAMILY TABLE 5-1: CONFIGURATION BITS AND DEVICE IDS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300000h(1,8) CONFIG1L — — USBDIV CPUDIV1 CPUDIV0 PLLDIV2 PLLDIV1 PLLDIV0 300001h CONFIG1H IESO FCMEN 300002h CONFIG2L — — 300003h CONFIG2H — — 300005h CONFIG3H MCLRE — 300006h CONFIG4L DEBUG XINST — Default/ Unprogrammed Value --00 0000 00-- 0111 — FOSC3 FOSC2 FOSC1 FOSC0 BORV1 BORV0 BOREN1 BOREN0 PWRTEN — WDTPS3 WDTPS2 WDTPS1 W
PIC18F2XXX/4XXX FAMILY TABLE 5-2: DEVICE ID VALUES Device ID Value Device DEVID2 Legend: Note 1: 2: DEVID1 PIC18F2221 21h 011x xxxx PIC18F2321 21h 001x xxxx PIC18F2410 11h 011x xxxx PIC18F2420 11h 010x xxxx(1) PIC18F2423 11h 010x xxxx(2) PIC18F2450 24h 001x xxxx PIC18F2455 12h 011x xxxx PIC18F2458 2Ah 011x xxxx PIC18F2480 1Ah 111x xxxx PIC18F2510 11h 001x xxxx PIC18F2515 0Ch 111x xxxx PIC18F2520 11h 000x xxxx(1) PIC18F2523 11h 000x xxxx(2) PIC18F2525 0Ch 110x xxx
PIC18F2XXX/4XXX FAMILY TABLE 5-2: DEVICE ID VALUES (CONTINUED) Device ID Value Device DEVID2 Legend: Note 1: 2: DEVID1 PIC18F4620 0Ch 000x xxxx PIC18F4680 0Eh 100x xxxx PIC18F4682 27h 010x xxxx PIC18F4685 27h 011x xxxx The ‘x’s in DEVID1 contain the device revision code. DEVID1 bit 4 is used to determine the device type (REV4 = 0). DEVID1 bit 4 is used to determine the device type (REV4 = 1).
PIC18F2XXX/4XXX FAMILY TABLE 5-3: Bit Name PIC18F2XXX/4XXX FAMILY BIT DESCRIPTIONS (CONTINUED) Configuration Words Description USBDIV CONFIG1L USB Clock Selection bit (PIC18F2455/2550/4455/4550, PIC18F2458/2553/4458/4553 and PIC18F2450/4450 devices only) Selects the clock source for full-speed USB operation: 1 = USB clock source comes from the 96 MHz PLL divided by 2 0 = USB clock source comes directly from the OSC1/OSC2 oscillator block; no divide CPUDIV<1:0> CONFIG1L CPU System Clock Selection
PIC18F2XXX/4XXX FAMILY TABLE 5-3: Bit Name PIC18F2XXX/4XXX FAMILY BIT DESCRIPTIONS (CONTINUED) Configuration Words Description WDPS<3:0> CONFIG2H Watchdog Timer Postscaler Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 WDTEN CONFIG2H Watchdog Timer Enable bit 1 = WDT is enabled 0 = WDT is disabled (control is placed on the SWD
PIC18F2XXX/4XXX FAMILY TABLE 5-3: Bit Name PIC18F2XXX/4XXX FAMILY BIT DESCRIPTIONS (CONTINUED) Configuration Words Description ICPRT CONFIG4L Dedicated In-Circuit (ICD/ICSP™) Port Enable bit (PIC18F2455/2550/4455/4550, PIC18F2458/2553/4458/4553 and PIC18F2450/4450 devices only) 1 = ICPORT is enabled 0 = ICPORT is disabled BBSIZ<1:0>(1) CONFIG4L Boot Block Size Select bits (PIC18F2585/2680/4585/4680 devices only) 11 = 4K words (8 Kbytes) Boot Block 10 = 4K words (8 Kbytes) Boot Block 01 = 2K words
PIC18F2XXX/4XXX FAMILY TABLE 5-3: Bit Name PIC18F2XXX/4XXX FAMILY BIT DESCRIPTIONS (CONTINUED) Configuration Words Description CP2 CONFIG5L Code Protection bit (Block 2 code memory area) 1 = Block 2 is not code-protected 0 = Block 2 is code-protected CP1 CONFIG5L Code Protection bit (Block 1 code memory area) 1 = Block 1 is not code-protected 0 = Block 1 is code-protected CP0 CONFIG5L Code Protection bit (Block 0 code memory area) 1 = Block 0 is not code-protected 0 = Block 0 is code-protected C
PIC18F2XXX/4XXX FAMILY TABLE 5-3: Bit Name PIC18F2XXX/4XXX FAMILY BIT DESCRIPTIONS (CONTINUED) Configuration Words Description EBTR5 CONFIG7L Table Read Protection bit (Block 5 code memory area) (PIC18F2685 and PIC18F4685 devices only) 1 = Block 5 is not protected from Table Reads executed in other blocks 0 = Block 5 is protected from Table Reads executed in other blocks EBTR4 CONFIG7L Table Read Protection bit (Block 4 code memory area) (PIC18F2682/2685 and PIC18F4682/4685 devices only) 1 = Blo
PIC18F2XXX/4XXX FAMILY 5.3 Single-Supply ICSP Programming The LVP bit in Configuration register, CONFIG4L, enables Single-Supply (Low-Voltage) ICSP Programming. The LVP bit defaults to a ‘1’ (enabled) from the factory. If Single-Supply Programming mode is not used, the LVP bit can be programmed to a ‘0’ and RB5/PGM becomes a digital I/O pin. However, the LVP bit may only be programmed by entering the High-Voltage ICSP mode, where MCLR/VPP/RE3 is raised to VIHH.
PIC18F2XXX/4XXX FAMILY TABLE 5-4: Device DEVICE BLOCK LOCATIONS AND SIZES Memory Size Pins (Bytes) PIC18F2221 4K 28 PIC18F2321 8K 28 Ending Address Boot Block 0001FF Size (Bytes) Block 0 Block 1 Block 2 Block 3 Block 4 Block 5 0007FF 000FFF — — — — 0003FF 000FFF 001FFF — — — — 0003FF 0001FF 0007FF Boot Block Block 0 512 1536 1024 1024 512 3584 1024 3072 2048 2048 Remaining Device Blocks Total 2048 4096 4096 8192 PIC18F2410 16K 28 0007FF 001FFF 003FFF — — — — 20
PIC18F2XXX/4XXX FAMILY TABLE 5-4: Device DEVICE BLOCK LOCATIONS AND SIZES (CONTINUED) Memory Size Pins (Bytes) Ending Address Boot Block Size (Bytes) Block 0 Block 1 Block 2 Block 3 Block 4 Block 5 Boot Block Block 0 Remaining Device Blocks Total PIC18F4455 24K 40 0007FF 001FFF 003FFF 005FFF — — — 2048 6144 16384 24576 PIC18F4458 24K 40 0007FF 001FFF 003FFF 005FFF — — — 2048 6144 16384 24576 2048 6144 4096 4096 8192 16384 PIC18F4480 16K 40 PIC18F4510 32K 40 PIC18F4
PIC18F2XXX/4XXX FAMILY TABLE 5-5: CONFIGURATION WORD MASKS FOR COMPUTING CHECKSUMS Configuration Word (CONFIGxx) 1L Device 1H 2L 2H 3L 3H 4L 4H 5L 5H 6L 6H 7L 7H Address (30000xh) 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh PIC18F2221 00 CF 1F 1F 00 87 F5 00 03 C0 03 E0 03 40 PIC18F2321 00 CF 1F 1F 00 87 F5 00 03 C0 03 E0 03 40 PIC18F2410 00 CF 1F 1F 00 87 C5 00 03 C0 03 E0 03 40 PIC18F2420 00 CF 1F 1F 00 87 C5 00 03 C0 03
PIC18F2XXX/4XXX FAMILY TABLE 5-5: CONFIGURATION WORD MASKS FOR COMPUTING CHECKSUMS (CONTINUED) Configuration Word (CONFIGxx) 1L Device 1H 2L 2H 3L 3H 4L 4H 5L 5H 6L 6H 7L 7H Address (30000xh) 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh PIC18F4620 00 CF 1F 1F 00 87 C5 00 0F C0 0F E0 0F 40 PIC18F4680 00 CF 1F 1F 00 86 C5 00 0F C0 0F E0 0F 40 PIC18F4682 00 CF 1F 1F 00 86 C5 00 3F C0 3F E0 3F 40 PIC18F4685 00 CF 1F 1F 00 86 C5 00
PIC18F2XXX/4XXX FAMILY AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE 6.0 Standard Operating Conditions Operating Temperature: 25C is recommended Param No. Sym Characteristic Min Max Units Conditions VIHH High-Voltage Programming Voltage on MCLR/VPP/RE3 VDD + 4.0 12.5 V (Note 2) D110A VIHL Low-Voltage Programming Voltage on MCLR/VPP/RE3 2.00 5.50 V (Note 2) D111 Supply Voltage During Programming 2.00 5.
PIC18F2XXX/4XXX FAMILY AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE (CONTINUED) 6.0 Standard Operating Conditions Operating Temperature: 25C is recommended Param No.
PIC18F2XXX/4XXX FAMILY NOTES: DS39622L-page 44 2010 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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