Datasheet

PIC18F47J53 FAMILY
DS39964B-page 574 Preliminary  2010 Microchip Technology Inc.
Associated Registers, Reception ......................366
Associated Registers, Transmission................. 365
Reception.......................................................... 366
Transmission..................................................... 365
Extended Instruction Set
ADDFSR ...................................................................502
ADDULNK................................................................. 502
CALLW......................................................................503
MOVSF .....................................................................503
MOVSS ..................................................................... 504
PUSHL ......................................................................504
SUBFSR ...................................................................505
SUBULNK ................................................................. 505
External Clock Input ............................................................ 38
F
Fail-Safe Clock Monitor............................................. 441, 455
Interrupts in Power-Managed Modes ........................ 457
POR or Wake-up From Sleep ................................... 457
WDT During Oscillator Failure .................................. 456
Fast Register Stack............................................................. 85
Firmware Instructions........................................................459
Flash Program Memory..................................................... 109
Associated Registers ................................................118
Control Registers ...................................................... 110
EECON1 and EECON2 .................................... 110
TABLAT (Table Latch) Register........................ 112
TBLPTR (Table Pointer) Register.....................112
Erase Sequence ....................................................... 114
Erasing......................................................................114
Operation During Code-Protect ................................ 118
Reading..................................................................... 113
Table Pointer
Boundaries Based on Operation....................... 112
Table Pointer Boundaries ......................................... 112
Table Reads and Table Writes .................................109
Write Sequence ........................................................115
Writing....................................................................... 115
Unexpected Termination...................................118
Write Verify .......................................................118
FSCM. See Fail-Safe Clock Monitor.
G
GOTO................................................................................ 480
H
Hardware Multiplier ...........................................................119
8 x 8 Multiplication Algorithms .................................. 119
Operation ..................................................................119
Performance Comparison (table)..............................119
High/Low-Voltage Detect .................................................. 419
Applications...............................................................423
Associated Registers ................................................424
Characteristics ..........................................................532
Current Consumption................................................ 421
Effects of a Reset......................................................424
Operation ..................................................................420
During Sleep .....................................................424
Setup......................................................................... 421
Start-up Time ............................................................ 421
Typical Application .................................................... 423
I
I/O Ports............................................................................ 141
Open-Drain Outputs.................................................. 142
Pin Capabilities .........................................................141
TTL Input Buffer Option ............................................ 142
I
2
C Mode........................................................................... 310
I
2
C Mode (MSSP)
Acknowledge Sequence Timing ............................... 338
Associated Registers ................................................ 344
Baud Rate Generator ............................................... 331
Bus Collision
During a Repeated Start Condition................... 342
During a Stop Condition ................................... 343
Clock Arbitration ....................................................... 333
Clock Stretching........................................................ 325
10-Bit Slave Receive Mode (SEN = 1) ............. 325
10-Bit Slave Transmit Mode ............................. 325
7-Bit Slave Receive Mode (SEN = 1) ............... 325
7-Bit Slave Transmit Mode ............................... 325
Clock Synchronization and CKP bit .......................... 326
Effects of a Reset ..................................................... 339
General Call Address Support .................................. 329
I
2
C Clock Rate w/BRG.............................................. 332
Master Mode............................................................. 329
Operation.......................................................... 331
Reception ......................................................... 335
Repeated Start Condition Timing ..................... 334
Start Condition Timing ...................................... 333
Transmission .................................................... 335
Multi-Master Communication, Bus Collision
and Arbitration .................................................. 339
Multi-Master Mode.................................................... 339
Operation.................................................................. 315
Read/Write
Bit Information (R/W Bit)................ 315, 318
Registers .................................................................. 310
Serial Clock (SCLx Pin) ............................................ 318
Slave Mode............................................................... 315
Addressing........................................................ 315
Addressing Masking Modes
5-Bit .......................................................... 316
7-Bit .......................................................... 317
Reception ......................................................... 318
Transmission .................................................... 318
Sleep Operation........................................................ 339
Stop Condition Timing .............................................. 338
INCF ................................................................................. 480
INCFSZ............................................................................. 481
In-Circuit Debugger........................................................... 458
In-Circuit Serial Programming (ICSP)....................... 441, 458
Indexed Literal Offset Addressing
and Standard PIC18 Instructions.............................. 506
Indexed Literal Offset Mode.............................................. 506
Indirect Addressing ........................................................... 104
INFSNZ............................................................................. 481
Initialization Conditions for All Registers....................... ??–80
Instruction Cycle ................................................................. 86
Clocking Scheme........................................................ 86
Flow/Pipelining............................................................ 86
Instruction Set................................................................... 459
ADDLW..................................................................... 465
ADDWF..................................................................... 465
ADDWF (Indexed Literal Offset Mode)..................... 507
ADDWFC .................................................................. 466
ANDLW..................................................................... 466
ANDWF..................................................................... 467
BC............................................................................. 467
BCF .......................................................................... 468
BN............................................................................. 468
BNC .......................................................................... 469