Datasheet

PIC18F47J53 FAMILY
DS39964B-page 542 Preliminary  2010 Microchip Technology Inc.
FIGURE 31-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
TABLE 31-20: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param
No.
Symbol Characteristic Min Max Units Conditions
73 T
DIV2SCH,
T
DIV2SCL
Setup Time of SDIx Data Input to SCKx Edge 35 — ns V
DD = 3.3V,
V
DDCORE = 2.5V
100 — ns V
DD = 2.15V,
V
DDCORE = 2.15V
73A TB2B Last Clock Edge of Byte 1 to the 1st Clock
Edge of Byte 2
1.5 TCY + 40 — ns
74 T
SCH2DIL,
T
SCL2DIL
Hold Time of SDIx Data Input to SCKx Edge 30 — ns V
DD = 3.3V,
V
DDCORE = 2.5V
83 — ns VDD = 2.15V
75 T
DOR SDOx Data Output Rise Time — 25 ns PORTB or PORTC
76 T
DOF SDOx Data Output Fall Time — 25 ns PORTB or PORTC
78 TSCR SCKx Output Rise Time (Master mode) — 25 ns PORTB or PORTC
79 T
SCF SCKx Output Fall Time (Master mode) — 25 ns PORTB or PORTC
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SDIx
73
74
75, 76
78
79
79
78
MSb LSb
bit 6 - - - - - - 1
MSb In
LSb In
bit 6 - - - - 1
Note: Refer to Figure 31-4 for load conditions.