Datasheet

PIC18F47J53 FAMILY
DS39964B-page 540 Preliminary  2010 Microchip Technology Inc.
TABLE 31-17: ENHANCED CAPTURE/COMPARE/PWM REQUIREMENTS
FIGURE 31-10: PARALLEL MASTER PORT READ TIMING DIAGRAM
Param
No.
Symbol Characteristic Min Max Units Conditions
50 T
CCL ECCPx Input Low Time No prescaler 0.5 TCY + 20 — ns
With prescaler 10 — ns
51 T
CCH ECCPx Input High Time No prescaler 0.5 TCY + 20 — ns
With prescaler 10 — ns
52 TCCP ECCPx Input Period
3 T
CY + 40
N
—nsN = prescale
value (1, 4 or 16)
53 TCCR ECCPx Output Fall Time — 25 ns
54 T
CCF ECCPx Output Fall Time — 25 ns
3 T
CY
40+
N
----------------------------
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2
System
PMALL/PMALH
PMD<7:0>
Address
PMA<13:18>
Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C unless otherwise stated.
PMWR
PMCS<2:1>
PMRD
Clock
PM2
PM3
PM6
PM7
PM5
PM1
Data
Address<7:0>