Datasheet

 2010 Microchip Technology Inc. Preliminary DS39964B-page 535
PIC18F47J53 FAMILY
TABLE 31-10: EXTERNAL CLOCK TIMING REQUIREMENTS
TABLE 31-11: PLL CLOCK TIMING SPECIFICATIONS (VDDCORE = 2.35V TO 2.75V)
TABLE 31-12: INTERNAL RC ACCURACY (INTOSC AND INTRC SOURCES)
Param.
No.
Symbol Characteristic Min Max Units Conditions
1A F
OSC External CLKI Frequency
(1)
DC 48 MHz EC Oscillator mode
DC 48 ECPLL Oscillator mode
(2)
Oscillator Frequency
(1)
4 16 MHz HS Oscillator mode
416
(4)
HSPLL Oscillator mode
(3)
1TOSC External CLKI Period
(1)
20.8 — ns EC Oscillator mode
20.8 — ECPLL Oscillator mode
(2)
Oscillator Period
(1)
62.5 250 ns HS Oscillator mode
62.5
(4)
250 HSPLL Oscillator mode
(3)
2TCY Instruction Cycle Time
(1)
83.3 DC ns TCY = 4/FOSC, Industrial
3TOSL,
T
OSH
External Clock in (OSC1)
High or Low Time
10 — ns EC Oscillator mode
4T
OSR,
T
OSF
External Clock in (OSC1)
Rise or Fall Time
— 7.5 ns EC Oscillator mode
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
2: In order to use the PLL, the external clock frequency must be either 4, 8, 12, 16, 20, 24, 40 or 48 MHz.
3: In order to use the PLL, the crystal/resonator must produce a frequency of either 4, 8, 12 or 16 MHz.
4: This is the maximum crystal/resonator driver frequency. The internal FOSC frequency when running from
the PLL can be up to 48 MHz.
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
F10 F
OSC Oscillator Frequency Range 4 — 48 MHz
F11 FSYS On-Chip VCO System Frequency — 96 — MHz
F12 t
rc
PLL Start-up Time (lock time) — — 2 ms
Param
No.
Device Min Typ Max Units Conditions
INTOSC Accuracy @ Freq = 8 MHz,
4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz, 31 kHz
(1)
All Devices
-1 +
0.15 +1 % 0°C to +85°C VDD = 2.4V-3.6V
V
DDCORE = 2.3V-2.7V
-1 +0.25 +1 % -40°C to +85°C VDD = 2.0V-3.6V
V
DDCORE = 2.0V-2.7V
INTRC Accuracy @ Freq = 31 kHz
(1)
All Devices 20.3 — 42.2 kHz -40°C to +85°C VDD = 2.0V-3.6V
V
DDCORE = 2.0V-2.7V
Note 1: The accuracy specification of the 31 kHz clock is determined by which source is providing it at a given time.
When INTSRC (OSCTUNE<7>) is ‘1’, use the INTOSC accuracy specification. When INTSRC is ‘0’, use
the INTRC accuracy specification.