Datasheet

PIC18F47J53 FAMILY
DS39964B-page 154 Preliminary  2010 Microchip Technology Inc.
TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
RC6/CCP9/
PMA5/TX1/
CK1/RP17
RC6 1 I ST PORTC<6> data input.
0 O DIG LATC<6> data output.
CCP9 1 I ST Capture input.
0 O DIG Compare/PWM output.
PMA5
(2)
1 I ST/TTL Parallel Master Port io_addr_in<5>.
0 O DIG Parallel Master Port address.
TX1 0 O DIG Asynchronous serial transmit data output (EUSART
module); takes priority over port data. User must configure
as an output.
CK1 1 I ST Synchronous serial clock input (EUSART module).
0 O DIG Synchronous serial clock output (EUSART module); takes
priority over port data.
RP17 1 I ST Remappable Peripheral Pin 17 input.
0 O DIG Remappable Peripheral Pin 17 output.
RC7/CCP10/
PMA4/RX1/
DT1/SDO1/
RP18
RC7 1 I ST PORTC<7> data input.
0 O DIG LATC<7> data output.
CCP10 1 I ST Capture input.
0 O DIG Compare/PWM output.
PMA4
(2)
x I/O ST/TTL/
DIG
Parallel Master Port address.
RX1 1 I ST Asynchronous serial receive data input (EUSART module).
DT1 1 1 ST Synchronous serial data input (EUSART module). User
must configure as an input.
0 O DIG Synchronous serial data output (EUSART module); takes
priority over port data.
SDO1 0 O DIG SPI data output (MSSP1 module).
RP18 1 I ST Remappable Peripheral Pin 18 input.
0 O DIG Remappable Peripheral Pin 18 output.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PORTC RC7 RC6 RC5 RC4
— RC2 RC1 RC0
LATC LATC7 LATC6 — — — LATC2 LATC1 LATC0
TRISC TRISC7 TRISC6
— — — TRISC2 TRISC1 TRISC0
ANCON1 VBGEN — — PCFG12 PCFG11 PCFG10 PCFG9 PCFG8
CM2CON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0
UCON
— PPBRST SE0 PKTDIS USBEN RESUME SUSPND —
UCFG UTEYE UOEMON — UPUEN UTRDIS FSEN PPB1 PPB0
RTCCFG RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0
TABLE 10-7: PORTC I/O SUMMARY
(1)
(CONTINUED)
Pin Function
TRIS
Setting
I/O
I/O
Type
Description
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
input/output; I
2
C/SMB = I
2
C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or
is overridden for this option)
Note 1: Enhanced PWM output is available only on PIC18F4XJ53 devices.
2: This bit is only available on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and
PIC18LF47J53).