Datasheet

PIC18F47J13 FAMILY
DS39974A-page 552 Preliminary  2010 Microchip Technology Inc.
Operation in Power-Managed Modes ...................... 300
Registers .................................................................. 293
Serial Clock .............................................................. 292
Serial Data In ........................................................... 292
Serial Data Out ......................................................... 292
Slave Mode ..............................................................298
Slave Select .............................................................292
Slave Select Synchronization ................................... 298
SPI Clock ................................................................. 297
SSPxBUF Register ...................................................297
SSPxSR Register .....................................................297
Typical Connection ...................................................296
SSPOV ............................................................................. 335
SSPOV Status Flag .......................................................... 335
SSPxSTAT Register
R/W
Bit ............................................................. 315, 318
SSx
................................................................................... 292
Stack Full/Underflow Resets .............................................. 85
SUBFSR ........................................................................... 479
SUBFWB .......................................................................... 468
SUBLW ............................................................................469
SUBULNK ........................................................................479
SUBWF ............................................................................ 469
SUBWFB ..........................................................................470
SWAPF ............................................................................470
T
Table Pointer Operations (table) ......................................110
Table Reads/Table Writes .................................................. 85
T
AD ................................................................................... 375
TBLRD ............................................................................. 471
TBLWT .............................................................................472
Timer0 ..............................................................................205
Associated Registers ...............................................207
Operation ................................................................. 206
Overflow Interrupt ..................................................... 207
Prescaler .................................................................. 207
Switching Assignment ......................................207
Prescaler Assignment (PSA Bit) .............................. 207
Prescaler Select (T0PS2:T0PS0 Bits) ...................... 207
Reads and Writes in 16-Bit Mode ............................206
Source Edge Select (T0SE Bit) ................................ 206
Source Select (T0CS Bit) ......................................... 206
Timer1 ..............................................................................209
16-Bit Read/Write Mode ...........................................213
Associated Registers ...............................................218
Clock Source Selection ............................................ 211
Gate ......................................................................... 215
Interrupt ....................................................................214
Operation ................................................................. 211
Oscillator .......................................................... 209, 213
Layout Considerations ..................................... 214
Resetting, Using the ECCP
Special Event Trigger .......................................215
TMR1H Register ......................................................209
TMR1L Register ....................................................... 209
Use as a Clock Source .............................................214
Timer2 ..............................................................................219
Associated Registers ...............................................220
Interrupt ....................................................................220
Operation ................................................................. 219
Output ......................................................................220
PR2 Register ............................................................266
TMR2 to PR2 Match Interrupt ..................................266
Timer3/5 ........................................................................... 221
16-Bit Read/Write Mode .......................................... 226
Associated Registers ............................................... 231
Gate ......................................................................... 226
Operation ................................................................. 225
Oscillator ...........................................................221, 226
Overflow Interrupt .............................................221, 230
Special Event Trigger (ECCP) ................................. 230
TMRxH Register ...................................................... 221
TMRxL Register ....................................................... 221
Timer4
TMRx to PRx Match Interrupt .................................. 234
Timer4/6/8 ........................................................................ 233
Associated Registers ............................................... 235
Interrupt ................................................................... 234
MSSP Clock Shift .................................................... 234
Operation ................................................................. 233
Output ...................................................................... 234
Postscaler. See Postscaler, Timer4/6/8.
Prescaler. See Prescaler, Timer4/6/8.
PRx Register ............................................................ 233
TMRx Register ......................................................... 233
TMRx to PRx Match Interrupt .................................. 233
Timing Diagrams
A/D Conversion ........................................................ 527
Asynchronous Reception ......................................... 358
Asynchronous Transmission .................................... 356
Asynchronous Transmission (Back-to-Back) ........... 356
Automatic Baud Rate Calculation ............................ 354
Auto-Wake-up Bit (WUE) During
Normal Operation ............................................ 359
Auto-Wake-up Bit (WUE) During Sleep ................... 359
Baud Rate Generator with Clock Arbitration ............ 333
BRG Overflow Sequence
......................................... 354
BRG Reset Due to SDAx Arbitration During
Start Condition ................................................. 341
Bus Collision During a Repeated
Start Condition (Case 1) .................................. 342
Bus Collision During a Repeated
Start Condition (Case 2) .................................. 342
Bus Collision During a Start
Condition (SCLx = 0) ....................................... 341
Bus Collision During a Stop Condition (Case 1) ...... 343
Bus Collision During a Stop Condition (Case 2) ...... 343
Bus Collision During Start
Condition (SDAx Only) ..................................... 340
Bus Collision for Transmit and Acknowledge .......... 339
CLKO and I/O .......................................................... 510
Clock Synchronization ............................................. 326
Clock/Instruction Cycle .............................................. 86
Enhanced Capture/Compare/PWM ......................... 514
Enhanced PWM Output (Active-High) ..................... 276
Enhanced PWM Output (Active-Low) ...................... 277
EUSARTx Synchronous Receive (Master/Slave) .... 526
EUSARTx Synchronous Transmission
(Master/Slave) ................................................. 526
Example SPI Master Mode (CKE = 0) ..................... 518
Example SPI Master Mode (CKE = 1) ..................... 519
Example SPI Slave Mode (CKE = 0) ....................... 520
Example SPI Slave Mode (CKE = 1) ....................... 521
External Clock .......................................................... 508
Fail-Safe Clock Monitor ........................................... 429
First Start Bit ............................................................ 333
Full-Bridge PWM Output .......................................... 280
Half-Bridge PWM Output ..................................278, 285