Datasheet

 2010 Microchip Technology Inc. Preliminary DS39974A-page 521
PIC18F47J13 FAMILY
FIGURE 30-16: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
TABLE 30-24: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol Characteristic Min Max Units Conditions
70 T
SSL2SCH,
T
SSL2SCL
SSx
 to SCKx  or SCKx  Input 3 TCY —ns
70A T
SSL2WB SSx to Write to SSPxBUF 3 TCY —ns
71 T
SCH SCKx Input High Time
(Slave mode)
Continuous 1.25 TCY + 30 — ns
71A Single byte 40 — ns (Note 1)
72 T
SCL SCKx Input Low Time
(Slave mode)
Continuous 1.25 TCY + 30 — ns
72A Single byte 40 — ns (Note 1)
73 T
DIV2SCH,
T
DIV2SCL
Setup Time of SDIx Data Input to SCKx Edge 25 — ns
73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)
74 T
SCH2DIL,
T
SCL2DIL
Hold Time of SDIx Data Input to SCKx Edge 35 — ns V
DD = 3.3V,
V
DDCORE = 2.5V
100 — ns VDD = 2.15V
75 T
DOR SDOx Data Output Rise Time — 25 ns
76 T
DOF SDOx Data Output Fall Time — 25 ns
77 TSSH2DOZSSx  to SDOx Output High-Impedance 10 70 ns
80 T
SCH2DOV,
T
SCL2DOV
SDOx Data Output Valid after SCKx Edge — 50 ns V
DD = 3.3V,
V
DDCORE = 2.5V
—100nsV
DD = 2.15V
81 T
DOV2SCH,
T
DOV2SCL
SDOx Data Output Setup to SCKx Edge T
CY —ns
82 T
SSL2DOV SDOx Data Output Valid after SSx  Edge — 50 ns
83 T
SCH2SSH,
T
SCL2SSH
SSx
 after SCKx Edge 1.5 TCY + 40 — ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
SSx
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SDI
70
71 72
82
SDIx
74
75, 76
MSb bit 6 - - - - - - 1 LSb
77
bit 6 - - - - 1 LSb In
80
83
Note: Refer to Figure 30-4 for load conditions.
73
MSb In