Datasheet

PIC18F47J13 FAMILY
DS39974A-page 48 Preliminary  2010 Microchip Technology Inc.
TABLE 4-1: LOW-POWER MODES
4.1.3 CLOCK TRANSITIONS AND STATUS
INDICATORS
The length of the transition between clock sources is
the sum of two cycles of the old clock source and three
to four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Two bits indicate the current clock source and its
status: OSTS (OSCCON<3>) and SOSCRUN
(OSCCON2<6>). In general, only one of these bits will
be set in a given power-managed mode. When the
OSTS bit is set, the primary clock would be providing
the device clock. When the SOSCRUN bit is set, the
Timer1 oscillator would be providing the clock. If neither
of these bits is set, INTRC would be clocking the
device.
4.1.4 MULTIPLE SLEEP COMMANDS
The power-managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN and DSEN bits at the time the instruction is exe-
cuted. If another SLEEP instruction is executed, the
device will enter the power-managed mode specified
by IDLEN and DSEN at that time. If IDLEN or DSEN
have changed, the device will enter the new
power-managed mode specified by the new setting.
Mode
DSCONH<7> OSCCON<7,1:0> Module Clocking
Available Clock and Oscillator Source
DSEN
(1)
IDLEN
(1)
SCS<1:0> CPU Peripherals
Sleep 00N/A Off Off Timer1 oscillator and/or RTCC may optionally be
enabled
Deep
Sleep
(3)
10N/A Powered
off
(2)
Powered off RTCC can run uninterrupted using the Timer1 or
internal low-power RC oscillator
PRI_RUN 0 N/A 00 Clocked Clocked The normal, full-power execution mode; primary
clock source (defined by FOSC<2:0>)
SEC_RUN 0 N/A 01 Clocked Clocked Secondary – Timer1 oscillator
RC_RUN 0 N/A 11 Clocked Clocked Postscaled internal clock
PRI_IDLE 0100Off Clocked Primary clock source (defined by FOSC<2:0>)
SEC_IDLE 0101Off Clocked Secondary – Timer1 oscillator
RC_IDLE 0111Off Clocked Postscaled internal clock
Note 1: IDLEN and DSEN reflect their values when the SLEEP instruction is executed.
2: Deep Sleep turns off the internal core voltage regulator to power down core logic. See Section 4.6 “Deep Sleep
Mode” for more information.
3: Deep Sleep mode is only available on “F” devices, not “LF” devices.
Note: Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep or Deep
Sleep mode, or one of the Idle modes,
depending on the setting of the IDLEN bit.