Datasheet

 2010 Microchip Technology Inc. Preliminary DS39974A-page 27
PIC18F47J13 FAMILY
PORTC (continued)
RC6/CCP9/PMA5/TX1/CK1/RP17
RC6
CCP9
PMA5
TX1
CK1
RP17
44
(3)
44
(3)
I/O
I/O
I/O
O
I/O
I/O
ST/DIG
ST/DIG
DIG
ST/TTL/
DIG
ST/DIG
ST/DIG
Digital I/O.
Capture/Compare/PWM input/output.
Parallel Master Port address.
EUSART1 asynchronous transmit.
EUSART1 synchronous clock (see related
RX1/DT1).
Remappable Peripheral Pin 17 input/output.
RC7/CCP10/PMA4/RX1/DT1/RP18
RC7
CCP10
PMA4
RX1
DT1
RP18
1
(3)
1
(3)
I/O
I/O
I/O
I
I/O
I/O
ST/DIG
ST/DIG
ST/TTL/
DIG
ST
ST/DIG
ST/DIG
Digital I/O.
Capture/Compare/PWM input/output.
Parallel Master Port address.
EUSART1 asynchronous receive.
EUSART Synchronous data (see related
TX1/CK1).
Remappable Peripheral Pin 18 input/output.
TABLE 1-4: PIC18F4XJ13 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
44-
QFN
44-
TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
DIG = Digital output I
2
C™ = Open-Drain, I
2
C specific
Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
2: Available only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13).
3: 5.5V tolerant.