Datasheet

 2010 Microchip Technology Inc. Preliminary DS39974A-page 187
PIC18F47J13 FAMILY
REGISTER 11-9: PMADDRH: PARALLEL PORT ADDRESS REGISTER HIGH BYTE
(MASTER MODES ONLY) (ACCESS F6Fhh)
(1)
U0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— CS1 Parallel Master Port Address High Byte<13:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ r = Reserved
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 CS1: Chip Select bit
If PMCON
<7:6> = 10:
1 = Chip select is active
0 = Chip select is inactive
If PMCON<7:6> =
11 or 00:
Bits function as ADDR<14>.
bit 5-0 Parallel Master Port Address: High Byte<13:8> bits
Note 1: In Enhanced Slave mode, PMADDRH functions as PMDOUT1H, one of the Output Data Buffer registers.
REGISTER 11-10: PMADDRL: PARALLEL PORT ADDRESS REGISTER LOW BYTE
(MASTER MODES ONLY) (ACCESS F6Eh)
(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Parallel Master Port Address Low Byte<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ r = Reserved
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 Parallel Master Port Address: Low Byte<7:0> bits
Note 1: In Enhanced Slave mode, PMADDRL functions as PMDOUT1L, one of the Output Data Buffer registers.