Information

PIC18F47J13 FAMILY
DS80503E-page 4  2011 Microchip Technology Inc.
4. Module: Master Synchronous Serial Port
(MSSP)
In Master I
2
C Receive mode, if a Stop condition
occurs in the middle of an address or data
reception, the SCL clock stream will continue
endlessly and the RCEN bit of the SSPxCON2
register will remain improperly set. When a Start
condition occurs after the improper Stop condi-
tion, nine additional clocks will be generated,
followed by the RCEN bit going low.
Work around
Use low-impedance pull-ups on the SDA line to
reduce the possibility of noise glitches that may
trigger an improper Stop event. Use a time-out
event timer to detect the unexpected Stop con-
dition, and subsequently, the stuck RCEN bit.
Clear the stuck RCEN bit by clearing the SSPEN
bit of SSPxCON1.
Affected Silicon Revisions
5. Module: Master Synchronous Serial Port
When configured for I
2
C™ slave reception, the MSSP
module may not receive the correct data, in extremely
rare cases. This occurs only if the Serial Receive/
Transmit Buffer register (SSPxBUF) is not read after
the SSP1IF interrupt (PIR1<3>) has occurred, but
before the first rising clock edge of the next byte being
received.
Work around
The issue can be resolved in either of these ways:
• Prior to the I
2
C slave reception, enable the
clock stretching feature. This is done by setting
the SEN bit (SSPxCON2<0>).
• Each time the SSPxIF is set, read the
SSPxBUF before the first rising clock edge of
the next byte being received.
Affected Silicon Revisions
6. Module: Enhanced Universal
Synchronous Asynchronous
Receiver Transmitter (EUSART)
In rare situations, when interrupts are enabled,
unexpected results may occur if:
• The EUSART is disabled (SPEN bit
(RCSTAx<7>) = 0)
• The EUSART is re-enabled (RCSTAx<7> = 1)
• A two-cycle instruction is executed immediately
after setting SPEN, CREN or TXEN = 1
Work around
Add a 2 TCY delay after any instruction that re-
enables the EUSART module (sets SPEN, CREN
or TXEN = 1).
See Example 1.
Affected Silicon Revisions
EXAMPLE 1: RE-ENABLING AN EUSART MODULE
A1
X
A1
X
A1
X
;Initial conditions: SPEN = 0 (module disabled)
;To re-enable the module:
;Re-Initialize TXSTAx, BAUDCONx, SPBRGx, SPBRGHx registers (if needed)
;Re-Initialize RCSTAx register (if needed), but do not set SPEN = 1 yet
;Now enable the module, but add a 2-Tcy delay before executing any two-cycle
;instructions
bsf RCSTA1, SPEN ;or RCSTA2 if EUSART2
nop ;1 Tcy delay
nop ;1 Tcy delay (two total)
;CPU may now execute 2 cycle instructions