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PIC18F47J13 FAMILY

DS80503E-page 10  2011 Microchip Technology Inc.

5. Module: Special Features of the CPU

Flash memory devices (PIC18F46J13,

PIC18F26J13), it is necessary to write WPFP6

(CONFIG4L<6>) with ‘0’ to maintain correct

operation of the write-protect feature.

At the time of this writing, MPLAB

tools may

incorrectly maintain the WPFP6 bit as ‘1’ on

64-Kbyte devices. To force MPLAB to write

CONFIG4L with the corrected values, refer to

Code Examples 1 and 2.

EXAMPLE 1: C18

EXAMPLE 2: MPASM™

only valid when WPDIS = 0.

would cause the WPCFG bit to be ignored.

The corrected register definitions are as follows:

#pragma romdata config_section = 0xFFFE

const rom unsigned char config4l = 0xB0;

#pragma code

ORG 0xFFFE

config4l_and_4h db 0xB0, 0xF3

R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1

WPCFG WPFP6

(2)

WPFP5 WPFP4 WPFP3 WPFP2 WPFP1 WPFP0

bit 7 bit 0

Legend:

R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 WPCFG: Write/Erase Protect Configuration Region Select bit

1 = Configuration Words page is not erase/write-protected unless WPEND and WPFP<6:0> settings

protect the Configuration Words page

(1)

0 = Configuration Words page is erase/write-protected, regardless of WPEND and WPFP<6:0>

(1)

bit 6-0 WPFP<6:0>: Write/Erase Protect Page Start/End Location bits

Used with the WPEND bit to define which pages in Flash will be erase/write-protected.

Note 1: The “Configuration Words page” contains the FCWs and is the last page of implemented Flash memory on

a given device. Each page consists of 1,024 bytes. For example, on a device with 64 Kbytes of Flash, the

first page is 0 and the last page (Configuration Words page) is 63 (3Fh).

2: This bit must always be written with ‘0’ on 64K Flash devices for proper operation.