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Table Of Contents

 2011 Microchip Technology Inc. DS80503E-page 1

PIC18F47J13 FAMILY

The PIC18F47J13 family devices that you have

received conform functionally to the current Device

Data Sheet (DS39974A), except for the anomalies

described in this document.

The silicon issues discussed in the following pages are

for silicon revisions with the Device and Revision IDs

listed in Table 1. The silicon issues are summarized in

Table 2.

The errata described in this document will be addressed

in future revisions of the PIC18F47J13 family silicon.

Data Sheet clarifications and corrections start on page 5,

following the discussion of silicon issues.

The silicon revision level can be identified using the

current version of MPLAB

IDE and Microchip’s pro-

grammers, debuggers, and emulation tools, which are

available at the Microchip corporate web site

(www.microchip.com).

For example, to identify the silicon revision level using

MPLAB IDE in conjunction with MPLAB ICD 2 or

PICkit™ 3:

1. Using the appropriate interface, connect the

device to the MPLAB ICD 2 programmer/

debugger or PICkit™ 3.

2. From the main menu in MPLAB IDE, select

Configure>Select Device

, and then select the

target part number in the dialog box.

3. Select the MPLAB hardware tool

(Debugger>Select Tool

4. Perform a “Connect” operation to the device

(Debugger>Connect

). Depending on the devel-

opment tool used, the part number and Device

Revision ID value appear in the Output window.

The DEVREV values for the various PIC18F47J13 family

silicon revisions are shown in Table 1.

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated in the last column of

Table 2 apply to the current silicon

revision (A1).

Note: If you are unable to extract the silicon

revision level, please contact your local

Microchip sales office for assistance.

TABLE 1: SILICON DEVREV VALUES

Part Number Device ID

(1)

Revision ID for Silicon Revision

(2)

PIC18F47J13 2CFh

01h

PIC18F46J13 2CDh

PIC18F27J13 2CBh

PIC18F26J13 2C9h

PIC18LF47J13 2DFh

PIC18LF46J13 2DDh

PIC18LF27J13 2DBh

PIC18LF26J13 2D9h

Note 1: The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration

memory space. They are shown in hexadecimal in the format, “DEVID DEVREV”.

2: Refer to the “PIC18F2XJXX/4XJXX Family Flash Microcontroller Programming Specification” (DS39687)

for detailed information on Device and Revision IDs for your specific device.

PIC18F47J13 Family

Silicon Errata and Data Sheet Clarification

Summary of content (14 pages)

PAGE 1
PIC18F47J13 FAMILY PIC18F47J13 Family Silicon Errata and Data Sheet Clarification The PIC18F47J13 family devices that you have received conform functionally to the current Device Data Sheet (DS39974A), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2.
PAGE 2
PIC18F47J13 FAMILY TABLE 2: SILICON ISSUE SUMMARY Module Feature Item Number Affected Revisions(1) Issue Summary A1 CTMU Constant Current Source 1. Oscillator Configurations PLL 2. PLL can not be enabled unless the 8 or 4 MHz INTOSC option is set. X ADC A/D 3. ANx pin may output a pull-up pulse during acquisition. X MSSP I2C™ Mode 4. If a Stop condition occurs in the middle of an address or data reception, there will be issues with the SCL clock stream and RCEN bit.
PAGE 3
PIC18F47J13 FAMILY Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (A1). 1. Module: Charge Time Measurement Unit (CTMU) When using the CTMU, the constant current source may not output if the internal band gap reference is not enabled.
PAGE 4
PIC18F47J13 FAMILY 4. Module: Master Synchronous Serial Port (MSSP) 2 In Master I C Receive mode, if a Stop condition occurs in the middle of an address or data reception, the SCL clock stream will continue endlessly and the RCEN bit of the SSPxCON2 register will remain improperly set. When a Start condition occurs after the improper Stop condition, nine additional clocks will be generated, followed by the RCEN bit going low.
PAGE 5
PIC18F47J13 FAMILY Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS39974A): Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. Note: On “LF” devices, the VCAP/VDDCORE pin must be tied to a voltage supply at the VDDCORE level. Refer to Section 30.0 “Electrical Characteristics” for information on VDD and VDDCORE.
PAGE 6
PIC18F47J13 FAMILY CONSIDERATIONS FOR CERAMIC CAPACITORS In recent years, large value, low-voltage, surface mount ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. The low-ESR, small physical size and other properties make ceramic capacitors very attractive in many types of applications. Ceramic capacitors are suitable for use with the internal voltage regulator of this microcontroller.
PAGE 7
PIC18F47J13 FAMILY 2. Module: Reset 3. Module: Electrical Characteristics Register 20-1 and Register 20-5 incorrectly define the SSPxSTAT Reset state as ‘1111 1111’. The correct Reset state of the SSPxSTAT is ‘0000 0000’. Changes, shown in bold, have been made to the D060, D061 and D063 rows in Section 30.4 DC Characteristics: PIC18F47J13 Family (Industrial). The updated table is shown below: 30.
PAGE 8
PIC18F47J13 FAMILY 4. Module: Electrical Characteristics The code in Example 20-2 does not set up the PPS registers correctly to map the SPI2 pins out to the RB<2:0> pins. The corrected code example, with changes in bold, is shown below. EXAMPLE 20-2: 512-BYTE SPI MASTER MODE Init AND TRANSFER ;For this example, let's use RP5(RB2) for SCK2, ;RP4(RB1) for SDO2, and RP3(RB0) for SDI2 ;Let's use SPI master mode, CKE = 0, CKP = 0, ;without using slave select signalling.
PAGE 9
PIC18F47J13 FAMILY EXAMPLE 20-2: 512-BYTE SPI MASTER MODE Init AND TRANSFER (CONTINUED) ;Somewhere else in our project, lets assume we have ;allocated some RAM for use as SPI receive and ;transmit buffers.
PAGE 10
PIC18F47J13 FAMILY 5. Module: Special Features of the CPU Register 27-7 omitted Footnote 2. On 64-Kbyte Flash memory devices (PIC18F46J13, PIC18F26J13), it is necessary to write WPFP6 (CONFIG4L<6>) with ‘0’ to maintain correct operation of the write-protect feature. At the time of this writing, MPLAB® tools may incorrectly maintain the WPFP6 bit as ‘1’ on 64-Kbyte devices. To force MPLAB to write CONFIG4L with the corrected values, refer to Code Examples 1 and 2.
PAGE 11
PIC18F47J13 FAMILY REGISTER 27-8: CONFIG4H: CONFIGURATION REGISTER 4 HIGH (BYTE ADDRESS 300007h) U-1 U-1 U-1 U-1 U-0 U-0 R/WO-1 R/WO-1 — — — — — — WPEND WPDIS bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Program the corresponding Flash Configuration bit to ‘1’ bit 3-2 Unimplemented: Read as ‘0’ bit 1 WPEND: Write-Protect Disable bit
PAGE 12
PIC18F47J13 FAMILY APPENDIX A: DOCUMENT REVISION HISTORY Rev A Document (6/2010) Initial release of this document. Added silicon issues 1 (Charge Time Measurement Unit – CTMU), 2 (Phase Locked Loop – PLL). 3 (Analog-to-Digital Converter – ADC), 4 (Master Synchronous Serial Port – MSSP), 5 (Master Synchronous Serial Port – MSSP) and 6 (Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)).
PAGE 13
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 14
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