Datasheet

 2010 Microchip Technology Inc. Preliminary DS39974A-page 417

PIC18F47J13 FAMILY

R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1

DEBUG

XINST STVREN CFGPLLEN PLLDIV2 PLLDIV1 PLLDIV0 WDTEN

bit 7 bit 0

Legend:

R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 DEBUG

: Background Debugger Enable bit

1 = Background debugger is disabled; RB6 and RB7 are configured as general purpose I/O pins

0 = Background debugger is enabled; RB6 and RB7 are dedicated to In-Circuit Debug

bit 6 XINST: Extended Instruction Set Enable bit

1 = Instruction set extension and Indexed Addressing mode are enabled

0 = Instruction set extension and Indexed Addressing mode are disabled

bit 5 STVREN: Stack Overflow/Underflow Reset Enable bit

1 = Reset on stack overflow/underflow is enabled

0 = Reset on stack overflow/underflow is disabled

bit 4 CFGPLLEN

: PLL Enable bit

1 = PLL is disabled until firmware sets the PLLEN bit at run time (OSCTUNE<6>)

0 = PLL is enabled at start-up

bit 3-1 PLLDIV<2:0>: Oscillator Selection bits

Divider must be configured to provide a 4 MHz input into the 96 MHz PLL. These bits have no effect

on 4x PLL operation.

111 = No divide – oscillator is used directly (4 MHz input)

110 = Oscillator divided by 2 (8 MHz input)

101 = Oscillator divided by 3 (12 MHz input)

100 = Oscillator divided by 4 (16 MHz input)

011 = Oscillator divided by 5 (20 MHz input)

010 = Oscillator divided by 6 (24 MHz input)

001 = Oscillator divided by 10 (40 MHz input)

000 = Oscillator divided by 12 (48 MHz input)

bit 0 WDTEN: Watchdog Timer Enable bit

1 = WDT is enabled

0 = WDT is disabled (control is placed on the SWDTEN bit)