Datasheet

PIC18F47J13 FAMILY
DS39974A-page 376 Preliminary  2010 Microchip Technology Inc.
22.5 A/D Conversions
Figure 22-3 displays the operation of the A/D Converter
after the GO/DONE
bit has been set and the
ACQT<2:0> bits are cleared. A conversion is started
after the following instruction to allow entry into Sleep
mode before the conversion begins.
Figure 22-4 displays the operation of the A/D Converter
after the GO/DONE
bit has been set. The ACQT<2:0>
bits are set to ‘010’ and are selecting a 4 T
AD
acquisition time before the conversion starts.
Clearing the GO/DONE
bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D conversion sample. This means the
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2T
AD Wait is required before the next acquisition can
be started. After this Wait, acquisition on the selected
channel is automatically started.
22.6 Use of the Special Event Triggers
A/D conversion can be started by the Special Event
Trigger of any of these modules:
• ECCP2 – Requires CCP2M<3:0> bits
(CCP2CON<3:0>) set at ‘1011’
• CTMU – Requires the setting of the CTTRIG bit
(CTMUCONH<0>)
• Timer1 Overflow
•RTCC Alarm
To start an A/D conversion:
• The A/D module must be enabled (ADON = 1)
• The appropriate analog input channel selected
• The minimum acquisition period is set in one of
these ways:
- Timing provided by the user
- Selection made of an appropriate T
ACQ time
With these conditions met, the trigger sets the
GO/DONE
bit and the A/D acquisition starts.
If the A/D module is not enabled (ADON = 0), the
module ignores the Special Event Trigger.
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Note: With an ECCP2 trigger, Timer1 or Timer3
is cleared. The timers reset to automati-
cally repeat the A/D acquisition period with
minimal software overhead (moving
ADRESH:ADRESL to the desired loca-
tion). If the A/D module is not enabled, the
Special Event Trigger is ignored by the
module, but the timer’s counter resets.
REGISTER 22-6: ADCTRIG: A/D TRIGGER REGISTER (BANKED EB8h)
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — TRIGSEL1 TRIGSEL0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-2 Unimplemented: Read as ‘0’
bit 1-0 TRIGSEL<1:0>: Special Trigger Select bits
11 = Selects the special trigger from the RTCC
10 = Selects the special trigger from the Timer1
01 = Selects the special trigger from the CTMU
00 = Selects the special trigger from the ECCP2