Datasheet

PIC18F47J13 FAMILY
DS39974A-page 356 Preliminary  2010 Microchip Technology Inc.
FIGURE 21-4: ASYNCHRONOUS TRANSMISSION
FIGURE 21-5: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
TABLE 21-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
PIR1
PMPIF
(1)
ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
PIE1 PMPIE
(1)
ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
IPR1
PMPIP
(1)
ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
PIR3
SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF
PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE
IPR3
SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP
RCSTAx
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
TXREGx EUSARTx Transmit Register
TXSTAx
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
BAUDCONx
ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN
SPBRGHx EUSARTx Baud Rate Generator Register High Byte
SPBRGx EUSARTx Baud Rate Generator Register Low Byte
ODCON2
— — — — CCP10OD CCP9OD U2OD U1OD
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Note 1: These bits are only available on 44-pin devices.
Word 1
Word 1
Transmit Shift Reg
Start bit bit 0 bit 1 bit 7/8
Write to TXREGx
BRG Output
(Shift Clock)
TXx (pin)
TXxIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
1 TCY
Stop bit
Word 1
Transmit Shift Reg.
Write to TXREGx
BRG Output
(Shift Clock)
TXx (pin)
TXxIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Word 2
Word 1
Word 2
Stop bit
Start bit
Transmit Shift Reg.
Word 1
Word 2
bit 0 bit 1
bit 7/8 bit 0
Note: This timing diagram shows two consecutive transmissions.
1 TCY
1 TCY
Start bit