Datasheet

PIC18F47J13 FAMILY
DS39974A-page 338 Preliminary  2010 Microchip Technology Inc.
20.5.12 ACKNOWLEDGE SEQUENCE
TIMING
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN
(SSPxCON2<4>). When this bit is set, the SCLx pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDAx pin. If the user wishes to
generate an Acknowledge, then the ACKDT bit should
be cleared. If not, the user should set the ACKDT bit
before starting an Acknowledge sequence. The BRG
then counts for one rollover period (T
BRG) and the SCLx
pin is deasserted (pulled high). When the SCLx pin is
sampled high (clock arbitration), the BRG counts for
T
BRG; the SCLx pin is then pulled low. Following this, the
ACKEN bit is automatically cleared, the BRG is turned
off and the MSSP module then goes into an inactive
state (Figure 20-25).
20.5.12.1 WCOL Status Flag
If the user writes the SSPxBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write does
not occur).
20.5.13 STOP CONDITION TIMING
A Stop bit is asserted on the SDAx pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPxCON2<2>). At the end of a
receive/transmit, the SCLx line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDAx line low. When the
SDAx line is sampled low, the BRG is reloaded and
counts down to 0. When the BRG times out, the SCLx
pin will be brought high and one Baud Rate Generator
rollover count (T
BRG) later, the SDAx pin will be
deasserted. When the SDAx pin is sampled high while
SCLx is high, the Stop bit (SSPxSTAT<4>) is set. A
T
BRG later, the PEN bit is cleared and the SSPxIF bit is
set (Figure 20-26).
20.5.13.1 WCOL Status Flag
If the user writes the SSPxBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write does
not occur).
FIGURE 20-25: ACKNOWLEDGE SEQUENCE WAVEFORM
FIGURE 20-26: STOP CONDITION RECEIVE OR TRANSMIT MODE
SDAx
SCLx
SSPxIF Set at
Acknowledge Sequence Starts Here,
Write to SSPxCON2,
ACKEN Automatically Cleared
Cleared in
TBRG
TBRG
the End of Receive
8
ACKEN = 1, ACKDT = 0
D0
9
SSPxIF
Software
SSPxIF Set at the End
of Acknowledge Sequence
Cleared in
Software
ACK
Note: TBRG = one Baud Rate Generator period.
SCLx
SDAx
SDAx Asserted Low before Rising Edge of Clock
Write to SSPxCON2,
Set PEN
Falling Edge of
SCLx = 1 for T
BRG, Followed by SDAx = 1 for TBRG
9th Clock
SCLx Brought High after T
BRG
TBRG
TBRG
after SDAx Sampled High, P bit (SSPxSTAT<4>) is Set
T
BRG
to Set up Stop Condition
ACK
P
T
BRG
PEN bit (SSPxCON2<2>) is Cleared by
Hardware and the SSPxIF bit is Set
Note: TBRG = one Baud Rate Generator period.