Datasheet

PIC18F47J13 FAMILY
DS39974A-page 272 Preliminary  2010 Microchip Technology Inc.
19.1 ECCP Outputs and Configuration
The Enhanced CCP module may have up to four PWM
outputs, depending on the selected operating mode.
These outputs, designated PxA through PxD, are
routed through the Peripheral Pin Select (PPS)
module. Therefore, individual functions can be mapped
to any of the remappable I/O pins (RPn).
The outputs that are active depend on the ECCP
operating mode selected. The pin assignments are
summarized in Table 19-3.
To configure the I/O pins as PWM outputs, the proper
PWM mode must be selected by setting the PxM<1:0>
and CCPxM<3:0> bits. The appropriate TRIS direction
bits for the port pins must also be set as outputs.
19.1.1 ECCP MODULE AND TIMER
RESOURCES
The ECCP modules use Timer1, 2, 3, 4, 6 or 8, depend-
ing on the mode selected. These timers are available to
CCP modules in Capture, Compare or PWM modes, as
shown in Table 19-1.
TABLE 19-1: ECCP MODE – TIMER
RESOURCE
The assignment of a particular timer to a module is
determined by the Timer to ECCP enable bits in the
CCPTMRS0 register (Register 19-2). The interactions
between the two modules are depicted in Figure 19-1.
Capture operations are designed to be used when the
timer is configured for Synchronous Counter mode.
Capture operations may not work as expected if the
associated timer is configured for Asynchronous Counter
mode.
19.2 Capture Mode
In Capture mode, the CCPRxH:CCPRxL register pair
captures the 16-bit value of the TMR1 or TMR3
registers when an event occurs on the corresponding
ECCPx pin. An event is defined as one of the following:
• Every falling edge
• Every rising edge
• Every fourth rising edge
•Every 16
th
rising edge
The event is selected by the mode select bits,
CCPxM<3:0> (CCPxCON register<3:0>). When a
capture is made, the interrupt request flag bit, CCPxIF,
is set (see Table 19-2). The flag must be cleared by
software. If another capture occurs before the value in
the CCPRxH/L register pair is read, the old captured
value is overwritten by the new captured value.
19.2.1 ECCP PIN CONFIGURATION
In Capture mode, the appropriate ECCPx pin should be
configured as an input by setting the corresponding
TRISx direction bit.
Additionally, the ECCPx input function needs to be
assigned to an I/O pin through the Peripheral Pin
Select module. For details on setting up the
remappable pins, see Section 10.7 “Peripheral Pin
Select (PPS)”.
ECCP Mode Timer Resource
Capture Timer1 or Timer3
Compare Timer1 or Timer3
PWM Timer2, Timer4, Timer6 or Timer8
TABLE 19-2: ECCP1/2/3 INTERRUPT FLAG
BITS
ECCP Module Flag-Bit
1 PIR1<2>
2 PIR2<0>
3 PIR4<0>
Note: If the ECCPx pin is configured as an out-
put, a write to the port can cause a capture
condition.