Datasheet

PIC18F47J13 FAMILY
DS39974A-page 266 Preliminary  2010 Microchip Technology Inc.
18.4 PWM Mode
In Pulse-Width Modulation (PWM) mode, the CCP4 pin
produces up to a 10-bit resolution PWM output. Since
the CCP4 pin is multiplexed with a PORTB data latch,
the appropriate TRISx bit must be cleared to make the
CCP4 pin an output.
Figure 18-3 shows a simplified block diagram of the
CCP1 module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 18.4.3
“Setup for PWM Operation”.
FIGURE 18-3: SIMPLIFIED PWM BLOCK
DIAGRAM
(2)
A PWM output (Figure 18-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 18-4: PWM OUTPUT
18.4.1 PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
EQUATION 18-1:
PWM frequency is defined as 1/[PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
•TMR2 is cleared
• The CCP4 pin is set
(An exception: If the PWM duty cycle = 0%, the
CCP4 pin will not be set)
• The PWM duty cycle is latched from CCPR4L into
CCPR4H
CCPR4L
CCPR4H (Slave)
Comparator
TMR2
Comparator
PR2
(Note 1)
R
Q
S
Duty Cycle Registers
CCP4CON<5:4>
Clear Timer,
CCP1 pin and
latch D.C.
TRISC<2>
RC2
Note 1: The 8-bit TMR2 value is concatenated with the 2-bit
internal Q clock, or 2 bits of the prescaler, to create
the 10-bit time base.
2: CCP4 and its appropriate timers are used as an
example. For details on all of the CCP modules and
their timer assignments, see Table 18-2 and
Table 18-3.
Note: The Timer2 postscalers (see Section 14.0
“Timer2 Module”) are not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)