Datasheet

 2010 Microchip Technology Inc. Preliminary DS39974A-page 225
PIC18F47J13 FAMILY
15.2 Timer3/5 Operation
Timer3 and Timer5 can operate in these modes:
•Timer
• Synchronous Counter
• Asynchronous Counter
• Timer with Gated Control
The operating mode is determined by the clock select
bits, TMRxCSx (TxCON<7:6>). When the TMRxCSx bits
are cleared (= 00), Timer3/5 increments on every internal
instruction cycle (FOSC/4). When TMRxCSx = 01, the
Timer3/5 clock source is the system clock (F
OSC), and
when it is ‘10’, Timer3/5 works as a counter from the
external clock from the TxCKI pin (on the rising edge after
the first falling edge) or the Timer1 oscillator.
FIGURE 15-1: TIMER3/5 BLOCK DIAGRAM
TMRxH TMRxL
TxSYNC
TxCKPS<1:0>
Prescaler
1, 2, 4, 8
0
1
Synchronized
Clock Input
2
Set Flag bit
TMRxIF on
Overflow
TMRx
(2)
TMRxON
Note 1: ST buffer is a high-speed type when using T1CKI.
2: Timerx registers increment on rising edge.
3: Synchronization does not operate while in Sleep.
TxG
T1OSC/SOSC
F
OSC/4
Internal
Clock
T1OSO/T1CKI
T1OSI
T
XOSCEN
1
0
TxCKI
TMRxCS<1:0>
(1)
Synchronize
(3)
det
Sleep Input
TMRxGE
0
1
00
01
10
11
From Timer4/6
Comparator 1
TxGPOL
D
Q
CK
Q
0
1
TxGVAL
TxGTM
Single Pulse
Acq. Control
TxGSPM
TxGGO/TxDONE
TxGSS<1:0>
EN
OUT
10
00
01
FOSC
Internal
Clock
Comparator 2
Output
Match PR4/6
R
D
EN
Q
Q1
RD
T3GCON
Data Bus
det
Interrupt
TMRxGIF
Set
TxCLK
FOSC/2
Internal
Clock
D
EN
Q
TxG_IN
TMRxON
Output
SOSCGO
T1OSCEN
T3OSCEN
T5OSCEN