Datasheet

 2010 Microchip Technology Inc. Preliminary DS39974A-page 223
PIC18F47J13 FAMILY
15.1 Timer3/5 Gate Control Register
The Timer3/5 Gate Control register (TxGCON),
provided in Register 14-2, is used to control the Timerx
gate.
REGISTER 15-2: TxGCON: TIMER3/5 GATE CONTROL REGISTER
(1)
(ACCESS F97h,
BANKED F21h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-x R/W-0 R/W-0
TMRxGE TxGPOL TxGTM TxGSPM TxGGO/TxDONE
TxGVAL TxGSS1 TxGSS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 TMRxGE: Timer Gate Enable bit
If TMRxON =
0:
This bit is ignored.
If TMRxON = 1:
1 = Timer counting is controlled by the Timerx gate function
0 = Timer counts regardless of the Timerx gate function
bit 6 TxGPOL: Gate Polarity bit
1 = Timer gate is active-high (Timerx counts when the gate is high)
0 = Timer gate is active-low (Timerx counts when the gate is low)
bit 5 TxGTM: Gate Toggle Mode bit
1 = Timer Gate Toggle mode is enabled.
0 = Timer Gate Toggle mode is disabled and toggle flip-flop is cleared
Timerx gate flip-flop toggles on every rising edge.
bit 4 TxGSPM: Timer Gate Single Pulse Mode bit
1 = Timer Gate Single Pulse mode is enabled and is controlling Timerx gate
0 = Timer Gate Single Pulse mode is disabled
bit 3 TxGGO/TxDONE
: Timer Gate Single Pulse Acquisition Status bit
1 = Timer gate single pulse acquisition is ready, waiting for an edge
0 = Timer gate single pulse acquisition has completed or has not been started
This bit is automatically cleared when TxGSPM is cleared.
bit 2 TxGVAL: Timer Gate Current State bit
Indicates the current state of the Timer gate that could be provided to TMRxH:TMRxL. Unaffected by the
Timer Gate Enable bit (TMRxGE).
bit 1-0 TxGSS<1:0>: Timer Gate Source Select bits
11 = Comparator 2 output
10 = Comparator 1 output
01 = TMR4/6 to match PR4/6 output
00 = T3G/T5G gate input pin
Note 1: Programming the TxGCON prior to TxCON is recommended.