Datasheet

 2010 Microchip Technology Inc. Preliminary DS39974A-page 137
PIC18F47J13 FAMILY
9.5 RCON Register
The RCON register contains bits used to determine the
cause of the last Reset or wake-up from Idle or Sleep
mode. RCON also contains the bit that enables
interrupt priorities (IPEN).
REGISTER 9-19: RCON: RESET CONTROL REGISTER (ACCESS FD0h)
R/W-0 U-0 R/W-1 R/W-1 R-1 R-1 R/W-0 R/W-0
IPEN
—CMRI TO PD POR BOR
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6 Unimplemented: Read as ‘0’
bit 5 CM:
Configuration Mismatch Flag bit
For details on bit operation, see Register 5-1.
bit 4 RI: RESET Instruction Flag bit
For details on bit operation, see Register 5-1.
bit 3 TO: Watchdog Timer Time-out Flag bit
For details on bit operation, see Register 5-1.
bit 2 PD: Power-Down Detection Flag bit
For details on bit operation, see Register 5-1.
bit 1 POR: Power-on Reset Status bit
For details on bit operation, see Register 5-1.
bit 0 BOR: Brown-out Reset Status bit
For details on bit operation, see Register 5-1.