Datasheet

PIC18F47J13 FAMILY
DS39974A-page 136 Preliminary  2010 Microchip Technology Inc.
REGISTER 9-17: IPR4: PERIPHERAL INTERRUPT PRIORITY REGISTER 4 (ACCESS F90h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
CCP10IP CCP9IP CCP8IP CCP7IP CCP6IP CCP5IP CCP4IP CCP3IP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-1 CCP10IP:CCP4IP: CCP<10:4> Interrupt Priority bits
1 =High priority
0 = Low priority
bit 0 CCP3IP: ECCP3 Interrupt Priority bit
1 =High priority
0 = Low priority
REGISTER 9-18: IPR5: PERIPHERAL INTERRUPT PRIORITY REGISTER 5 (ACCESS F99h)
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — CM3IP TMR8IP TMR6IP TMR5IP TMR5GIP TMR1GIP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5 CM3IP: Comparator 3 Interrupt Priority bit
1 =High priority
0 = Low priority
bit 4 TMR8IP: TMR8 to PR8 Match Interrupt Priority bit
1 =High priority
0 = Low priority
bit 3 TMR6IP: TMR6 to PR6 Match Interrupt Priority bit
1 =High priority
0 = Low priority
bit 2 TMR5IP: TMR5 Overflow Interrupt Priority bit
1 =High priority
0 = Low priority
bit 1 TMR5GIP: TMR5 Gate Interrupt Priority bit
1 =High priority
0 = Low priority
bit 0 TMR1GIP: TMR1 Gate Interrupt Priority bit
1 =High priority
0 = Low priority