Datasheet

2010 Microchip Technology Inc. Preliminary DS39974A-page 7
PIC18F47J13 FAMILY
Pin Diagrams (Continued)
28-Pin SPDIP/SOIC/SSOP
28-Pin QFN
Legend: RPn represents remappable pins.Some input and output functions are routed through the Peripheral Pin
Select (PPS) module and can be dynamically assigned to any of the RPn pins. For a list of the input and
output functions, see Table 10-13 and Table 10-14, respectively. For details on configuring the PPS module,
see Section 10.7 “Peripheral Pin Select (PPS)”.
Note: For the QFN package, it is recommended that the bottom pad be connected to V
SS.
PIC18F2XJ13
10
11
2
3
4
5
6
1
8
7
9
12
13
14
15
16
17
18
19
20
23
24
25
26
27
28
22
21
MCLR
RA0/AN0/C1INA/ULPWU/RP0
RA1/AN1/C2INA/V
BG/CTDIN/RP1
RA2/AN2/C2INB/C1IND/C3INB/V
REF-/CVREF
RA3/AN3/C1INB/VREF+
V
DDCORE/VCAP
RA5/AN4/C1INC/SS1/HLVDIN/RP2
V
SS1
OSC1/CLKI/RA7
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI/RP11
RC1/CCP8/T1OSI/RP12
RC2/AN11/C2IND/CTPLS/RP13
RC3/SCK1/SCL1/RP14
RB7/CCP7/KBI3/PGD/RP10
RB6/CCP6/KBI2/PGC/RP9
RB5/CCP5/KBI1/SDA2/RP8
RB4/CCP4/KBI0/SCL2/RP7
RB3/AN9/C3INA/CTED2/RP6
RB2/AN8/C2INC/CTED1/REFO/RP5
RB1/AN10/C3INC/RTCC/RP4
RB0/AN12/C3IND/INT0/RP3
V
DD
VSS2
RC7/CCP10/RX1/DT1/RP18
RC6/CCP9/TX1/CK1/RP17
RC5/SDO1/RP16
RC4/SDI1/SDA1/RP15
= Pins are up to 5.5V tolerant
10 11
2
3
6
1
18
19
20
21
22
12 13 14
15
8
7
16
17
232425262728
9
PIC18F2XJ13
RC0/T1OSO/T1CKI/RP11
5
4
RB7/CCP7/KBI3/PGD/RP10
RB6/CCP6/KBI2/PGC/RP9
RB5/CCP5/KBI1/SDA2/RP8
RB4/CCP4/KBI0/SCL2/RP7
RB3/AN9/C3INA/CTED2/RP6
RB2/AN8/C2INC/CTED1/REFO/RP5
RB1/AN10/C3INC/RTCC/RP4
RB0/AN12/C3IND/INT0/RP3
V
DD
VSS2
RC7/CCP10/RX1/DT1/RP18
RC6/CCP9/TX1/CK1/RP17
RC5/SDO1/RP16
RC4/SDI1/SDA1/RP15
MCLR
RA0/AN0/C1INA/ULPWU/RP0
RA1/AN1/C2INA/V
BG/CTDIN/RP1
RA2/AN2/C1INB/C1IND/C3INB/VREF-/CVREF
RA3/AN3/C1INB/VREF+
V
DDCORE/VCAP
RA5/AN4/C1INC/SS1/HLVDIN/RP2
V
SS1
OSC1/CLKI/RA7
OSC2/CLKO/RA6
RC1/CCP8/T1OSI/RP12
RC2/AN11/C2IND/CTPLS/RP13
RC3/SCK1/SCL1/RP14