Datasheet
PIC18F47J13 FAMILY
DS39974A-page 6 Preliminary 2010 Microchip Technology Inc.
Pin Diagrams (Continued)
44-Pin QFN
Legend: RPn represents remappable pins.Some input and output functions are routed through the Peripheral Pin
Select (PPS) module and can be dynamically assigned to any of the RPn pins. For a list of the input and
output functions, see Table 10-13 and Table 10-14, respectively. For details on configuring the PPS module,
see Section 10.7 “Peripheral Pin Select (PPS)”.
Note: For the QFN package, it is recommended that the bottom pad be connected to V
SS.
10
11
2
3
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
PIC18F4XJ13
37
RA3/AN3/C1INB/VREF+
RA2/AN2/C2INB/C1IND/C3INB/V
REF-/CVREF
RA1/AN1/C2INA/VBG/CTDIN/PMA7/RP1
RA0/AN0/C1INA/ULPWU/PMA6/RP0
MCLR
RB7/CCP7/KBI3/PGD/RP10
RB6/CCP6/KBI2/PGC/RP9
RB5/CCP5/PMA0/KBI1/RP8
RB4/CCP4/PMA1/KBI0/RP7
NC
RC6/CCP9/PMA5/TX1/CK1/RP17
RC5/SDO1/RP16
RC4/SDI1/SDA1/RP15
RD3/PMD3/RP20
RD2/PMD2/RP1
RD1/PMD1/SDA2
RD0/PMD0/SCL2
RC3/SCK1/SCL1/RP14
RC2/AN11/C2IND/CTPLS/RP13
RC1/CCP8/T1OSI/RP12
RC0/T1OSO/T1CKI/RP11
OSC2/CLKO/RA6
OSC1/CLKI/RA7
V
SS2
AV
DD2
RE2/AN7/PMCS
RE1/AN6/PMWR
RE0/AN5/PMRD
RA5/AN4/C1INC/SS1
/HLVDIN/RP2
V
DDCORE/VCAP
RC7/CCP10/PMA4/RX1/DT1/RP18
RD4/PMD4/RP21
RD5/PMD5/RP22
RD6/PMD6/RP23
V
SS1
V
DD1
RB0/AN12/C3IND/INT0/RP3
RB1/AN10/C3INC/PMBE/RTCC/RP4
RB2/AN8/C2INC/CTED1/PMA3/REFO/RP5
RB3/AN9/C3INA/CTED2/PMA2/RP6
RD7/PMD7/RP24
5
4
AVSS1
V
DD2
AV
DD1
= Pins are up to 5.5V tolerant